三維晶片(Three-dimensional Integrated Circuits) 使用矽穿通道(Through-Silicon Vias)
傳遞不同層間的訊號，具有低耗能、訊號傳遞距離縮短等好處，但矽穿通道的製造過程可
能會產生瑕疵而使訊號傳遞失敗，整顆晶片無法正常運作。為了提高三維晶片的良率，許
多論文提出了加入額外的矽穿通道，作為替代損壞的矽穿通道傳遞訊號，這些方法能有效
的解決常態分布之損壞矽穿通道。實務上可能發生由不同層晶片疊合時的錯位而造成損壞
的矽穿通道聚集在一起，前述的方法無法解決多個鄰近損壞的矽穿通道，用路由器連接的
容錯矽穿通道架構[1] 能處理這個問題，但該架構為了解決某些發生機率很低的損壞案例
而加入過多的硬體，使用了大量的晶片面積。在這份論文中提出了環狀連接的容錯矽穿通
道架構，更有效率的使用晶片面積，並在給定8 8 矽穿通道群與錯誤率1% 的假設條件
下，模擬出良率為98.47% ，雖然低於由路由器連接矽穿通道架構的良率99.00% ，卻能
降低54% 的晶片面積，除此之外，我們提出的架構能夠保證因重新繞道的訊號延遲不會
增加過多。

Three-dimensional Integrated Circuits (3D-ICs) that employ the Through-Silicon Vias
(TSVs) vertically stacking multiple dies provide many benefits, such as high density, high
bandwidth, low-power. However, the fabrication and bonding of TSVs may fail because of
many factors, such as the winding level of the thinned wafers, the surface roughness and
cleaness of silicon dies, and bonding technology. To improve the yield of 3D-ICs, many
redundant TSV architectures were proposed to repair 3D-ICs with faulty TSVs. These methods
reroute siganls of faulty TSVs to other regular or redundant TSVs. In practice, the faulty
TSVs may cluster because of imperfect bonding technology. To resolve the problem of clustered
TSV faults, router-based [1] redundant TSV architecture was the first paper proposed to
pay attention to this clustering problem. Their method enables faulty TSVs to be repaired
by redundant TSVs that are farther apart. However, for some rarely occurring defective
patterns, their method consumes too much area. In this paper, we propose a ring-based
redundant TSV architecture to utilize the area more efficiently as well as to maintain high
yield. Simulation results show that for a given number of TSVs (88) and TSV failure rate
(1%), our design achieves 54% area reduction of MUXes per signal, while the yield of our
ring-based redundant TSV architectures can still maintain 98.47% to 99.00% as compared
with router-based desgin [1]. Furthermore, the minimum shifting length of our ring-based
redundant TSV architecture is at most 1 which guarantees the minimum timing overhead of
each signal.

Contents
1 Introduction 2
2 Motivation 5
3 Proposed TSV Redundancy Architecture 9
3.1 Ring-based TSV Redundancy Architecture Design . . . . . . . . . . 9
3.2 Analysis of Nonrepairable Defect Patterns and Recovery Rate . . . 14
3.3 Repairing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Experimental Results 20
4.1 Comparison of Hardware Cost . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Recovery Rate Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Shifting Length Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Conclusion 26

[1] L. Jiang, Q. Xu, B. Eklow, “On effective TSV repair for 3D-stacked ICs,” DATE’12, pp. 793-798, March 2012.
[2] I. Koren and Z. Koren, “Defect tolerance in VLSI circuits: techniques and yield analysis,” Proc. of the IEEE, 86(9):
1819–1838, 1998.
[3] Y. Zhao, S. Khursheed, B. M. Al-Hashimi, “Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs,” ATS ’11,
pp. 201-206, November 2011.
[4] U. Kang, et al. “8 Gb 3-D DDR3 DRAM using through-silicon-via technology,” IEEE Journal of Solid-State Circuits,
45(1):111–119, January. 2010.
[5] A. Hsieh, T. Hwang, M. Chan, M. Tsai, C. Tseng, H. Li, “TSV Redundancy: Architecture and Design Issues in 3D IC,”
DATE’10, pp. 166-171, March 2012.
[6] A.V. Goldberg and S. Rao. “Beyond the flow decomposition barrier,” Journal of the ACM, 45(5):783–797, 1998.
[7] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, “Cu/Sn Microbumps
Interconnect for 3D TSV Chip Stacking”, Proceedings of Electronic Components and Technology Conference (ECTC’10),
pp. 858-863, 2010.
[8] N. Lin, J. Miao, P. Dixit, “Void formation over limiting current density and impurity analysis of TSV fabricated by
constant-current pulse-reverse modulation,” In Microelectronics Reliability, 2013.
[9] J.U. Knickerbocker, et al. “Three-dimensional silicon integration. IBM Journal of Research and Development”, 52(6):
553–569, November 2008.
[10] U. Kang, et al. “8 Gb 3-D DDR3 DRAM using through-silicon-via technology. IEEE Journal of Solid-State Circuits”,
45(1):111–119, Jan. 2010.
[11] I. Loi, et al. “A low-overhead fault tolerance scheme for TSV-based 3D network on chip links”, In Proc. Int’l Conf. on
Computer-Aided Design, pp. 598–602, 2008.
[12] D. H. Kim, S. Kim, S. K. Lin, “Impact of nano-scale through-silicon vias on the quality of today and future 3D IC
designs”, In Proc. SLiP, pp. 1-8, June 2011.
[13] “http://www.algorithmic-solutions.com”, LEDA Library
[14] R. Patti, “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs,” Proc. of the IEEE, vol.
84, no. 6, June 2006.
[15] A. W. Topol, J. D. C. La Tulipe, L. Shi, et al., “Three Dimensional Integrated Circuits,” IBM Journal of Research and
Development, vol. 50, no. 4/5, pp. 491-506, July/Sepetember 2006.
[16] C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated circuit yield statistics,” Proc. IEEE, vol. 71, pp.453 - 470,
1983.
[17] B. C. Arnold, “Pareto Distributions,” International Co-operative Publishing House, 1983
[18] Nangate, “The Nangate 45nm Open Cell Library,” http://www.nangate.com.
[19] L. Jiang, Y. Liu, L. Duan, Y. Xie, and Q. Xu, “Modeling TSV open defects in 3D-stacked DRAM,” ITC’10, pp. 1-9,
November 2010.
[20] N. Lin, J. Miao, P. Dixit, “Void formation over limiting current density and impurity analysis of TSV fabricated by
constant-current pulse-reverse modulation,” Microelectronics Reliability, vol. 53, pp. 1943-1953, 2013.
[21] K. H. Lu, S. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. S. Ho, “Thermal Stress Induced Delamination of Through
Silicon Vias in 3-D Interconnects,” ECTC’10, pp. 40-45, June 2010.
[22] Murphy, B.T., “Cost-Size Optima of Monolithic Integrated Circuits,” Proc. IEEE no. 12 vol. 52, pp. 1537–1545, 1964
[23] B. J. Ho, B. Nader, “A Generic Traffic Model for On-Chip Interconnection Networks,” The First International Workshop
on Networks-on-Chip Architectures, 2009
[24] Y. Kim, D. Han, O. Mutlu, M. Harchol-Balter, “ATLAS: A scalable and high-performance scheduling algorithm for
multiple memory controllers,” HPCA’10, pp. 1-12, January 2010.