|
[1] H. Chen, J. T. Chen, S. J. Lee, K. Chou, C. B. Chen, S. K. Hsu, H. C. Lin, C. N. Peng, and M. J. Wang, "Bandwidth Enhancement in 3DIC CoWoSTM Test Using Direct Probe Technology," Proc. Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012. [2] E. J. Marinissen, "Testing TSV-Based Three-Dimensional Stacked ICs," Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. [3] M. Taouil, S. Hamdioui and E. J. Marinissen, "How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs," Proc. Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011. [4] E. J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias," Proc. International Test Conference (ITC), 2009. [5] W. R. Bottoms, "Test Challenges for 3D Integration (an invited paper for CICC 2011)," Proc. Custom Integrated Circuits Conference (CICC), 2011. [6] R. T. Gu, C. Y. Ho, K. S. M. Li, Y. Ho, L. B. Chen, K. Y. Hsieh, J. J. Huang, B. C. Cheng, S. J. Wang and Z. H. Gao, "A layout-aware test methodology for silicon interposer in 3D System-in-a-Package," Proc. International Symposium on Next-Generation Electronics (ISNE), 2013. [7] R. Gonzalez and R. Woods, "Digital Image Processing," Addison Wesley, 1992.
|