帳號:guest(3.147.68.138)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):徐瑞祥
作者(外文):Hsu, Ruei-Siang
論文名稱(中文):堆疊前中介層之非接觸式晶片測試
論文名稱(外文):Contactless Stacked-die Testing for Pre-bond Interposers
指導教授(中文):張世杰
指導教授(外文):Chang, Shih-Chieh
口試委員(中文):吳文慶
黃婷婷
口試委員(外文):Wu, Wen-Ching
Hwang, TingTing
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:101062503
出版年(民國):103
畢業學年度:102
語文別:中文英文
論文頁數:24
中文關鍵詞:堆疊式晶片中介層測試熱影像
外文關鍵詞:Stacked-dieInterposerTestingThermal image
相關次數:
  • 推薦推薦:0
  • 點閱點閱:193
  • 評分評分:*****
  • 下載下載:5
  • 收藏收藏:0
一個堆疊式晶片之產品將多個晶片整合至中介層(interposer)上。在此論文中,我們首先討論傳統測試機制使用在中介層上的困難,接著我們提出一個可以使用在堆疊前(pre-bond)中介層上的非接觸式之測試機制以用來提升生產良率。我們的測試機制試圖從加熱中介層後之熱影像中偵測出損壞的中介層,我們從熱影像中擷取出特別的特徵(feature),並且使用一個分群演算法(clustering algorithm)來決定是否一個中介層為損壞。實驗結果證實出我們的測試機制可以顯著的將良率從70.5%提升至96.84%。
A stacked-die product integrates multiple dies on interposers. In this paper, we first discuss the difficulties of traditional testing mechanism for interposers. To improve production yield, a contactless testing mechanism for pre-bond interposers is proposed. Our testing mechanism attempts to detect a defective interposer from the thermal image after heating the interposer. We propose to extract special features from the thermal image and then use a clustering algorithm to determine whether the interposer is defective. Experimental results show that our testing mechanism can efficiently improve the yield from 70.5% to 96.84%.
List of Contents VII
List of Figures VIII
List of Tables IX
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PROPOSED TESTING FRAMEWORK 6
CHAPTER 3 FEATURE EXTRACTION OF INTERPOSER’S THERMAL IMAGES 8
3.1 Differential Second Derivative of Two Thermal Images 8
3.2 Feature Extraction 12
3.3 Applying Critical Features in Clustering Algorithm 16
CHAPTER 4 OVERALL CLUSTERING FLOW 17
CHAPTER 5 EXPERIMENTS 19
CHAPTER 6 CONCLUSIONS 23
REFERENCES 24
[1] H. Chen, J. T. Chen, S. J. Lee, K. Chou, C. B. Chen, S. K. Hsu, H. C. Lin, C. N. Peng, and M. J. Wang, "Bandwidth Enhancement in 3DIC CoWoSTM Test Using Direct Probe Technology," Proc. Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012.
[2] E. J. Marinissen, "Testing TSV-Based Three-Dimensional Stacked ICs," Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010.
[3] M. Taouil, S. Hamdioui and E. J. Marinissen, "How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs," Proc. Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011.
[4] E. J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias," Proc. International Test Conference (ITC), 2009.
[5] W. R. Bottoms, "Test Challenges for 3D Integration (an invited paper for CICC 2011)," Proc. Custom Integrated Circuits Conference (CICC), 2011.
[6] R. T. Gu, C. Y. Ho, K. S. M. Li, Y. Ho, L. B. Chen, K. Y. Hsieh, J. J. Huang, B. C. Cheng, S. J. Wang and Z. H. Gao, "A layout-aware test methodology for silicon interposer in 3D System-in-a-Package," Proc. International Symposium on Next-Generation Electronics (ISNE), 2013.
[7] R. Gonzalez and R. Woods, "Digital Image Processing," Addison Wesley, 1992.
(此全文限內部瀏覽)
電子全文
摘要檔
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *