矽穿孔技術 (Through Silicon Via, TSV) 是在三維晶片中的關鍵技術。然而，他可能有許多可靠度的問題。有許多文獻提出不同的容錯機制，用來提高良率，但是卻擁有過高的面積開銷成本。在本論文中，我們研究讓一組TSV只放一個備用TSV，在良率有一定以上並且符合時間約束的情況下，最優化備用TSV的數量使得增加的面積開銷最小。但是我們發現，這樣的問題可以通過約束圖分解證明此問題的時間複雜度是NP困難，所以我們用一種有效的啟發式搜索來解決這個問題。實驗證明我們的啟發式搜索比起其他啟發式搜索在同樣容錯機制下能夠減少最大62%的開銷

In three-dimensional integrated circuits (3D ICs), Through Silicon Via (TSV) is a critical enabling technique to provide vertical connections. However, it may suffer from many reliability issues such as undercut, misalignment or random open defects. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled as constrained graph decomposition problem, and prove its NP-hardness. Two efficient heuristics are further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 62%, compared with a seemingly more intuitive nearest-neighbor based heuristic.

List of Contents
List of Contents VI
List of Figures VII
List of Tables VIII
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 BACKGROUND AND MOTIVATION 5
CHAPTER 3 PPOBLEM FORMULATION 8
3.1 Chip Yield Constraint 15
3.2 Timing Constraint 15
CHAPTER 4 ALGORITHM 15
4.1 Symmetric distance constraint 15
4.1.1 Problem Modeling of Symmetry distance Constraint 15
4.1.2 Proof of NP-Hardness 19
4.1.3 Our Heuristic 24
4.2 Asymmetric distance constraint 31
4.2.1 Problem Modeling of asymmetric distance constrain 31
4.2.2 Our Heuristic 33
CHAPTER 5 EXPERIMENTAL RESULTS 38
CHAPTER 6 CONCLUSIONS 42
REFERENCES 43

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