於現代的VLSI layout design中，routability的評估變得越來越具有挑戰性。在這篇論文中提出一個新的track assignment方法，可利用global routing所提供的資訊來對routability進行更為精確的評估。這個方法首先利用greedy method來產生一個初步的結果，然後應用negotiation-based方式透過rip-up及re-assignment方法來改善結果。不同於之前的其他方法，在這篇論文中我們提出把local nets列入考慮範圍，並允許routing產生violations。在這種方式中，routing congestion的資訊不僅比global routing更為準確，而且也更接近於detailed routing。於實驗結果中可看出這篇論文能所提出有力的方法。

Routability estimation has become much more challenging for modern VLSI layout design. In this thesis a new approach for track assignment is presented, which utilizes global
routing information to estimate routability in a more accurate manner. It first uses a greedy method to generate an initial solution, and then applies a negotiation-based rip-up and re-assignment method to improve the result. Dierent from any prior work, the proposed approach takes local nets into account and allows the generation of routing
violations. In this way, the routing congestion information is not only more accurate than global routing but also closer to detailed routing. Experimental results are shown
to support the robustness of the proposed approach.

1 Introduction
2 Preliminaries and Problem Description
2.1 Local Net Extraction
2.2 Problem Formulation
2.3 Cost Metrics
2.3.1 Overlap Cost and Blockage Cost
2.3.2 Wire Length Cost
3 Initial Assignment
3.1 Assignment Order
3.2 Calculation of Wire Length Cost
3.3 Calculation of Overlap Cost and Blockage Cost
3.4 Overall Cost Function
4 Overlap Reduction
4.1 Rip-up Step
4.2 Re-assignment Step
4.3 History Cost
5 Experimental Results
5.1 Comparison between the Initial Assignment Stage and the Overlap Reduc-tion Stage
5.2 Comparison between a Prior Work and NTA
5.3 Iroute Ordering in Initial Assignment
5.4 Parallelism
5.5 Routability Estimation from Global Routing and Track Assignment
6 Conclusions and Future Work

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