隨著半導體技術的進步，電晶體的閘極長度可達奈米等級，在一顆積體電路上可放置幾十億顆電晶體，但由於製程技術上的物理限制，使得再將尺寸往下微縮漸行困難，摩爾定律 (Moore’s Law)也很難再持續。近年來，以矽穿孔 (TSV) 技術將多顆晶片堆疊形成三維積體電路的方法被提出，使得單位面積可放置更多的電晶體數目。三維動態隨機存取記憶體為一使用穿孔矽的應用，以Wide-I/O動態隨機存取記憶體(Wide-I/O DRAM)為例子，它是可使用穿孔矽堆疊多顆晶片達到記憶體大容量之目的，同時也具有多信號接腳的特徵，所以Wide-I/O DRAM比起現今的DRAM模組可使用較低的操作頻率就可達到相同的性能，達到高性能、低耗電之需求，因此適合用在行動裝置上。然而，自然生活中的粒子、宇宙幅射線，以及電路上的功率波動和熱雜訊，都會造成DRAM晶片上儲存的資料產生軟性錯誤，使得DRAM的可靠度隨著使用時間累積而迅速降低;在晶片與晶片的連接中，TSV、bumps、redistribution layers等等容易在製造或接合時產生缺陷，這也會使三維積體電路整體良率和可靠度降低。
本論文欲針對三維DRAM提出二級錯誤更正碼 (two-level EDAC)，除了保護記憶體晶片外，晶片與晶片間的連接上可能會發生的錯誤也可做資料更正，進而提升良率及可靠度。二級錯誤更正碼意指在記憶體控制器和記憶體晶片上都有錯誤更正碼之硬體設計，這可使每次資料藉由I/O傳輸資料後可更正一個錯，發生兩個錯時可被偵測到;資料從DRAM晶片讀出時也可更正一個錯，同樣也可偵測兩個錯。由於時間延遲問題對於Wide-I/O DRAM來說非常重要，我們的錯誤更正碼主要是以蕭碼 (Hsiao code)的演算法進行建碼，蕭碼在硬體設計上的複雜度低，使得在主要時間延遲控制上容易得到較小的結果。另外本論文也提出進一步減少蕭碼硬體主要延遲的方法，為了能夠減小面積，本論文將編碼和解碼器的硬體共享。最後實驗結果中展示及比較我們提出的各種蕭碼硬體的時間延遲和面積結果，在此使用90奈米製程。

With the progress of semiconductor technology entering the nano-meter scale, the scale of an integrated circuit is so big that it can house billions of transistors. Due to the physical limitation of process technology, scaling down is more difficult than before, and the Moore’s law is difficult to be maintained. As an alternative, through-silicon via (TSV) has been used for three-dimensional (3D) integration by stacking and bonding multiple dies in a single package. Three-dimensional DRAM is one of the popular applications using TSV to stack multiple memory dies for enlarging capacity. We take Wide-I/O DRAM, which is one type of 3D DRAM, for example. It has large number of I/O pins. With this feature, Wide-I/O DRAM can achieve the same performance of today’s DRAM module at much lower operating frequency. With these advantages, Wide-I/O DRAM is suitable for mobile device. However, DRAM dies are prone to soft errors due to alpha particles, cosmic radiation, power fluctuation, thermal noise, etc. Furthermore, the defects may occur in the inter-die interconnects (TSV, bumps, redistribution layers, etc.) due to manufacturing or bonding process. They decrease the yield and reliability of 3D DRAM.
In this work, we propose two-level error detection and correction (EDAC) scheme for 3D DRAM to protect memory dies and inter-die interconnects from soft errors and random defects. Our two-level EDAC means that the codec is implemented in both memory die and memory controller. Because timing is critical in 3D DRAM, we use Hsiao code due to its low complexity. We also propose a method that is adding extra parity bits for further reducing critical delay of codec. In order to reduce area, shared encoder and decoder is applied. We show post-layout simulation results of codec with a typical 90 nm CMOS technology.

Abstract i

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Error Detection and Correction Code for Memory . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Proposed Two Level Error Detection and Correction Scheme . . . . . . . . . . . . . . 3
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Fundamentals of Error Detection and Correction Code 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Systematic Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Hamming Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Single-Error Correction and Double-Error Detecting Code . . . . . . . . . . . . . . . . 9
2.5.1 Extended Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5.2 Hsiao Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Error Detection and Correction Code for Random Access Memory 14
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Conventional EDAC Implementation for Memory System . . . . . . . . . . . . . . . . 15
3.2.1 Generalized EDAC Design for Memory . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Encoding of Hsiao Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3 Decoding of Hsiao Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Performance Enhancement for Hsiao Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Reliability Enhancement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Partition of Codeword Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.2 Interleaved Structure for Burst-Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Two-Level Error Detection and Correction Scheme for 3D DRAM 25
4.1 Proposed Two-Level EDAC Scheme for 3D DRAM . . . . . . . . . . . . . . . . . . . . 26
4.1.1 Type 1 Two-Level EDAC for 3D DRAM . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.2 Type 2 Two-Level EDAC for 3D DRAM . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.3 Comparison of Type 1 and Type 2 Two-Level EDAC Scheme . . . . . . . 36
4.2 Pipeline Structure for Proposed Two-Level EDAC Scheme . . . . . . . . . . . . . . . 37
5 Experimental Results 41
5.1 Timing Analysis of Our Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Post-Layout Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Evaluation of Reliability by Mathematic Model . . . . . . . . . . . . . . . . . . . . . . . . . 49

6 Conclusions and Future Work 55
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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