近年來，由於醫學的快速發展，人類壽命得以延長。這使得生物醫學電子市
場快速成長，對於生理訊號量測系統的需求逐漸提高。在生理訊號量測系統中，
一高精密度之類比數位轉換器為一重要方塊，為了配合低速、高精密度的應用，
所以我們選擇三角積分類比數位轉換器作為資料轉換器之架構。為了配合計畫的
需求，本論文實現一可應用於生醫感測系統並處理所擷取生理訊號之三角積分調
變器。

本論文描述一個二階一位元離散時間三角積分調變器，透過TSMC 1P6M
0.18μm製程實現。使用單迴路回授架構可使得訊號轉移函數於高頻可有較佳濾
波效果，並使得調變器有較佳穩定性；運算放大器輸入級採用軌對軌架構，用以
提高於系統中之可靠度，使得積分器之輸出擺幅較大情況下，整體調變器仍可正
常運作。並於第一級積分器使用相關雙取樣技術，用來幫助降低放大器內元件不
匹配所造成的偏差並壓抑1/f雜訊。另外分別針對調變器中可能碰到之非理想效
應及系統之雜訊作分析與探討，由此得到所需之規格參數及部分電路細節之修改
。整個三角積分調變器操作在1.8V供電電壓，在20KHz的訊號頻寬、超取樣率
為256倍的情形下，所設計的調變器可以達到訊號對雜訊與諧波失真比為93.62
dB，相當於有效位元數15.26位元；整個電路的消耗功率為2.732 mW，效能指
標為1.782 pJ/conv.，核心佈局面積為668 x 278μm2。

In recent years , due to the rapid development of medical technology , human
Life is extended . This makes the rapid growth of biomedical electronic market , and
also let the needs of the physiological signals measurement systems promoted grad-
ually .A high precision analog-to-digital (A/D) converter is an important block in the
physiological signals measurement systems ; we generally choose the delta-sigma
A/D converter as the main architecture for the data converter . To be matching requ
irements for the plan , a delta-sigma modulator which is applied in the bio-sensing
system that could handle the signal capturing by the devices is implemented in this
thesis .

This thesis presents a one-bit second-order discrete-time delta-sigma modulator
(DT-ΔΣM) , and to be implemented with TSMC 0.18-μm 1P6M process . By using CIFB
architecture make the STF to have better filtering performance at high frequency ,
and make the modulator to have better stability ; the input stage of the operational
amplifier use the rail to rail architecture to raise the reliability of the system and ma-
ke the modulator still function work even though the outpu swing of the integrat-
or is larger . Also using the CDS technique in the first intergrator stage help to reduce
the offset of component mismatches and suppress the 1/f noise . The whole delta-
sigma modulator operating at 1.8V supply voltage , with 20KHz signal bandwidth ,
and oversampling ratio of 256 , the designed modulator achieved signal to noise and
distortion ratio(SNDR) of 93.26 dB , equivalent to the effective number of bits (ENOB
) 15.26 bits .The power consumption is 2.732 mW , the figure of merit (FoM) is 1.782
pJ/conv. , and the core chip area is 668 x 278μm2 .

中文摘要 I
ABSTRACT(英文摘要) II
目錄 III
圖目錄 VI
表目錄 X
第一章 序論 1
1.1研究動機 1
1.2論文章節組織 2
第二章 三角積分類比數位轉換器原理簡介 3
2.1類比數位轉換器分類 4
2.2尼奎斯特取樣理論簡介 5
2.3量化器(QUANTIZER)與量化雜訊 6
2.4性能指標(PERFORMANCE METRICS)[3][5] 9
2.4.1訊號雜訊比(SNR) 10
2.4.2訊號雜訊諧波比(SNDR) 10
2.4.3無雜散動態範圍(SFDR) 10
2.4.4動態範圍(DR) 11
2.4.5有效位元數(ENOB) 11
2.4.6過載準位(OL) 12
2.4.7指標參數(Figure of Merit，FOM) 12
2.5尼奎斯特取樣轉換器與超取樣轉換器性能之比較 13
2.6雜訊整形(NOISE SHAPING) 16
2.7三角積分類比數位轉換器基本分析 18
2.7.1基本結構 18
2.7.2低通與帶通(LP/BP) 19
2.7.3連續時間與離散時間(CT/DT) 20
2.7.3.a.離散時間與連續時間之架構簡介 20
2.7.3.b.內建抗混疊濾波器 21
2.7.3.c.離散時間和連續時間之比較 23
2.7.4一階 24
2.7.5二階 26
2.7.6高階 28
2.8穩定度 30
2.8.1李氏準則(Lee’s criterion) 30
2.8.2根軌跡(Root locus) 31
2.8.3頻帶外增益(out-of-band gain，OBG) 32
2.9三角積分調變器之主要結構分析 33
2.9.1單一位元(Single-bit)及多位元(Multi-bit)量化器 34
2.9.2單迴路串接積分器回授型(Cascade-of-integrators,feedback form，CIFB) 35
2.9.3單迴路串接積分器前饋型(Cascade-of-integrators,feedforward form，CIFF) 36
2.9.4局部回授架構 37
2.9.5多級串疊(multi-stage cascade) 39
第三章 系統架構分析規劃與模擬 41
3.1系統規格 41
3.2調變器架構選取 42
3.3三角積分調變器系統之線性模型 43
3.4交換電容積分器 48
3.4.1對於寄生電容不敏感之延遲型積分器(Parasitic-Insensitive Delay Integrator) 48
3.4.2積分器動態行為 49
3.5電路非理想效應考量 51
3.5.1雜訊源 51
3.5.1.a.熱雜訊(Thermal noise) 51
3.5.1.b.電晶體閃爍雜訊(Flicker noise) 53
3.5.2三角積分調變器中之雜訊分析 54
3.5.2.a.R-C低通濾波器之雜訊 54
3.5.2.b.取樣電路之雜訊 54
3.5.2.c.離散時間積分器電路之雜訊 55
3.5.2.d三角積分調變器中之雜訊 56
3.5.3開關相關議題 59
3.5.3.a有限導通電阻值(Finite turn-on-resistance) 59
3.5.3.b.通道電荷注入(Channel Charge injection)效應 60
3.5.3.c.時脈饋入(Clock Feedthrough)效應 60
3.5.3.d.改善電荷注入誤差之技術 61
3.5.4運算放大器非理想效應 64
3.5.4.a.有限直流增益(Finite DC gain) 64
3.5.4.b.迴轉率(Slew rate)與有限增益頻寬(Finite Gain-Bandwidth) 66
3.5.5系統及子電路方塊規格 70
第四章 電路分析與實現 71
4.1 CMOS傳輸閘開關(CMOS TRANSMISSION GATE SWITCH) 72
4.2運算放大器 73
4.2.1軌對軌常數轉導輸入級 74
4.2.2主要參數分析 76
4.3相關雙取樣積分器(CORRELATED DOUBLE SAMPLING INTEGRATOR) 79
4.4比較器與栓鎖器 81
4.5一位元回授DAC 83
4.6時脈產生器 84
4.7調變器 85
第五章 結論與未來工作 90
5.1結論 90
5.1未來工作 90
參考文獻 91

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