這篇論文提出一種用於穿矽連接孔的各階段測試方法，而這各階段測試方法其中包括堆疊前、堆疊中和堆疊後測試。推疊前的測試是要用來確認各個裸晶在堆疊前是否都是ㄧ個正常的裸晶，如此來增加最終的良率。堆疊中的測試則是要確保每一次的堆疊是否都有成功的堆疊，如果在堆疊中發現堆疊錯誤則不必繼續的往下堆疊。堆疊後的測試則是用來確認最終的堆疊是否有成功，如此複雜測試過程是目前對於3D IC的完整流程，但是目前比較少可以有一個簡單的方法可以完整的用於3D IC的測試流程，而我們的測試方法可以達到。
我們重複使用一樣的測試電路來達成我們的測試方法。在我們使用的測試結構中，我們將所有的測試單元以一個連一個的方式串接成全局震盪環，且使用daisy chain和TAP控制器來輔助我們的測試方法。藉由此方法我們可以簡化先前局部環的測試方法中遇到的測試結果檢索問題。雖然我們的方法無法在堆疊前的階段達到百分之百穿矽連接孔的故障位置覆蓋率，但是我們可以在堆疊後的階段做到。
而我們的測試方法會針對3D IC中的穿矽連接孔進行各種的參數性故障進行測試，分別是在穿矽連接孔中可能會造成額外延遲的open fault，我們會針對open fault所造成的大電阻和故障位置來分析，還有在穿矽連接孔中的leakage fault，同樣我們會針對leakage fault所造成的大電導和故障位置分析，最後則是會連接穿矽連接孔兩端的bridging fault，我們會針對bridging fault中連接兩端的電阻來分析。

This thesis presents an any-bond test method for TSV, and any-bond test means that including pre-bond, mid-bond, and post-bond test. We repeatedly use the same set of design-for-testability circuits to achieve our test method. In our test architecture, all the test wrappers are cascaded one after another to form a global ring oscillator, and we use daisy-chain and test access protocol controller to support our test method. By doing so, the test-result retrieval problem in previous local-ring based method can be alleviated. Even though our method can’t achieve the 100% fault location coverage for overall TSV in the pre-bond stage, we can do that in post-bond stage.

Content
Abstract i 摘要 ii 誌謝 iii
Content iv
List of Figures ................................................vi List of Tables........................................ viii Chapter 1 Introduction ................................ 1
1.1 Introduction....................................... 1

1.2 Thesis Organization ............................... 6

Chapter 2 Preliminaries................................ 7

2.1 Electrical Model of an TSV ........................ 7

2.2 Baseline Pre-Bond Test method ..................... 9

Chapter 3 ANY-BOND TEST METHOD......................... 11

3.1 Global-Ring Based Test Structure................... 11

3.2 Pre-Bond Test Flow ................................ 14

3.3 Post-Bond Test Flow ............................... 17

3.4 Clock Period Measurement........................... 20

3.5 Error Analysis for Clock Period Measurement Error ..23

3.6 Test Access Interface.............................. 26

Chapter 4 EXPERIMENTAL RESULTS......................... 29

4.1 Detection of Delay Faults ......................... 29

4.2 Detection of Leakage Faults ................................................ 34

4.3 Detection of Bridging Faults....................... 36

4.4 Area Overhead ..................................... 37

4.5 Test Time Analysis ................................ 38

Chapter 5 Conclusion................................... 40

Bibliography .......................................... 41

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