在三維晶片技術中，不同的晶片可經由穿矽連接孔連接，以堆曡的方式整合而成，其中有許多的穿矽連接孔是應用於晶片的電源接腳，將電源電壓傳送至各個晶片，而非應用於傳遞訊號。在已發表的文獻中，所提出的這些測試方法，還尚未深入探討關於電源電壓用穿矽連接孔的檢測技術。
在本篇論文裡，我們提出一個電源電壓用穿矽連接孔的測試架構與方法，在生產測試階段，藉由埋藏在電源電壓用穿矽連接孔的端點上，以環形震盪器為基礎的監測電路(建立在可調整的測試架構上，以因應大量的電源電壓用穿矽連接孔)，監測是否有過多的電源電壓落差。我們所提出方法的特色之一，採用[15]所發表的量測技術，可以監測動態的峰值電源電壓落差(藉由支援高取樣率的監測電路，比如1 GHz)，有別於先前同樣以環形震盪器為基礎監測電路的方法，只是監測一段長時間的平均電源電壓落差。為了提高測試結果的精準度，量測與資料分析，都應考量每個監測電路的製程變異，我們所提出方法的另一項關鍵特色，在資料分析的階段，先進行監測電路的製程變異校正，再分析資料的監測結果。檢測出這些發生在電源電壓傳遞網路上的微小缺陷是必要的，假使這些缺陷未被檢測出來，系統在運作的過程中，便可能因過多的電源電壓落差，發生一個短暫的時序故障。

Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this work, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (with a high sampling rate monitor, e.g., 1GHz), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.

Abstract i
摘要 ii
誌謝 iii
Content iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
Chapter 3 Proposed Method 7
3.1 Overall Test Architecture 7
3.2 Calibration scheme for Time-to-Digital Converter 10
3.3 Test Flow 12
3.4 Data Analytics 14
3.5 Operation 17
Chapter 4 Experimental Setup and Results for Detecting The Voltage Drop across A Defective TSV 19
4.1 Experimental Setup and Results 19
4.2 The Effect on The Process Calibration Scheme 22
4.3 Random Process Variation Case by Monte Carlo Simulation for 13-Stage Ring Oscillator 23
Chapter 5 Test Chip and Experimental Results of Fault Injection 24
5.1 Test Chip 24
5.2 Test Case Analyzing of The Test Chip 28
5.3 Area Overhead Estimation 30
5.4 Performance Comparison 31
Chapter 6 Conclusion 32
Bibliography 33

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