|
[1] L. L. Chang , Y. K. Choi , D. W. Ha , P. Ranade , S. Y. Xiong , J. Bokor , C. M. Hu and T. J. King, “Extremely scaled silicon nano-CMOS devices,” Proc. of the IEEE, Vol. 91, No. 11, Nov. 2003, pp. 1860-1873. [2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Sunderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50-nm FinFET: PMOS,” in Tech. Dig. Int. Electron Devices Meeting (IEDM), Nov. 1999, pp. 67-70. [3] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10nm Gate Length,” in Tech. Dig. Int. Electron Devices Meeting (IEDM), Dec. 2002, pp. 251-254. [4] E. J. Nowak , I. Aller , T. Ludwig , K. Kim , R. V. Joshi , C. T. Chuang , K. Bernstein and R. Puri, “Turning silicon on its edge double gate CMOS/FinFET technology,” IEEE Circuits Devices Mag., Vol. 20, No. 1, Feb. 2004, pp. 20-31. [5] Y. Liu, Q. Xu. “On Modeling Faults in FinFET Logic Circuits,” in Proc. IEEE Int. Test Conference (ITC), Nov. 2012, pp. 1-9. [6] E. Baravelli, A. Dixit, R. Rooyackers, M. Jurczak, N. Speciale and K. De Meyer , “Impact of line-edge roughness on FinFET matching performance,” IEEE Trans. Electron Devices, Vol. 54, No. 9, Sept. 2007, pp.2466 -2474. [7] V. H. Champac and V. Avendano, “Test of data retention faults in CMOS SRAMs using special DFT circuitries,” IEEE Circuits Devices Syst., Vol. 151, No. 2, April 2004, pp.78 -82. [8] S. Hamdioui and A. J. van de Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests,” in Proc. Ninth IEEE Asian Test Symp. (ATS), Dec. 2000, pp. 131-138. [9] A. Meixner and J. Banik “Weak write test mode: An SRAM cell stability design for test technique,” in Proc. Int. Test Conf., Nov. 1997, pp.1043-1052. [10] J. Yang, B. Wang, Y. Wu, and A. Ivanov, “Fast Detection of Data Retention Faults and Other SRAM Cell Open Defects,” in Proc. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 2006. pp. 167-180. [11] S. A. Tawfik , Z. Liu and V. Kursun, “Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability,” in Proc. Int. Conf. Microelectron. (ICM), Dec. 2007, pp.171-174. [12] Z. Liu, S. A. Tawfik, and V. Kursun, “An Independent-Gate FinFET SRAM Cell for High Data Stability and Enhanced Integration Density,” in Proc. IEEE International Systems on Chip (SOC) Conference, Sept. 2007, pp. 63-66. [13] [Online]. Available: ptm.asu.edu [14] A.J. van de Goor, “Testing Semiconductor Memories, Theory and Practice,” COMTEX Publishing, Gouda, The Netherlands, 1998. [15] E. Seevinck, F. J. List and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, Oct. 1987, pp. 748-754. [16] A. Bansal , S. Mukhopadhyay and K. Roy, “Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era”, IEEE Trans. Electron Devices, Vol. 54, No. 6, June 2007, pp.1409-1419. [17] Chih-Wea Wang, “FAME: An Advanced Memory Failure Analysis Framework”, National Tsing Hua University, 2003.
|