神經細胞藉由其自身之細胞膜電位進行訊號的編碼及傳遞，在膜電位變化的過程中離子通道的隨機開闔現象會隨之產生大量的低頻雜訊。由於離子通道隨機性的開關所造成的低頻雜訊頻譜，非常類似於電晶體由於介面陷阱產生低頻雜訊的機制。而此一低頻雜訊不僅不會對神經元間之溝通造成傷害，反而有助於神經元進行更穩健的訊號處理。隨著半導體製程的進步，電晶體尺寸不斷微縮，其低頻雜訊也不斷增強，影響了傳統積體電路的訊號處理的精確性。研究神經系統如何在低頻雜訊中進行訊號處理將可能使有助於改善目前積體電路設計之缺點。
若能在現有之神經細胞模型之中，加入雜訊可調變之電晶體，便可以產生類似神經細胞中之低頻雜訊。而研究這些雜訊所造成之影響便有助於神經系統在雜訊環境下之特性研究。於是如何在電路中使用雜訊可調變電晶體且不至於大幅影響原有電路特性變相當重要。
本論文選用了三種已證實具有雜訊可調變能力且使用CMOS標準製程之電晶體。由於不需要進行額外的製程調整，便可與現有神經細胞模型結合。並針對三種電晶體之結構以及直流電流特性進行分析，接著建立其直流電流模型。

Neurons encode and transmit information by changing its membrane potentials. The random opening and closing of ion channels in the process of membrane potential changing contributes to the 1/f noise spectrum. The 1/f noise caused by the random opening and closing of ion channels and which caused by the surface trap in the transistors are very similar. The 1/f noise is found to play a beneficial role rather than harmful role for neural communication. As the CMOS technology progressing, the transistor noise increases dramatically, and disturbs the accuracy of traditional VLSI signal processing. Studying how neural systems process the signal in 1/f noise may improve VLSI design.
Adding noise adaptable transistors into VLSI neuron model can model the 1/f noise in the neurons. Then studying how the effect caused by these noises contributes to study neuron systems in noisy environments. So how to use the noise adaptable transistor is become very important.
This thesis chooses three kinds of transistors using CMOS general process and the noise adaptability has been improved. Without additional process steps, they can be added to the existing neuron model. Then analysis the structure and the DC current characteristics of these transistors and build the DC current model.

致謝 I
摘要 III
Abstract V
目錄 VII
圖目錄 XI
表目錄 XVI
第一章 簡介 1
1.1 神經細胞與動作電位 2
1.2 神經細胞動作電位模型 6
1.2.1 積分刺激模型(Integrated-and-Fire Model) 7
1.2.2 霍奇金赫胥黎模型(Hodgkin-Huxley Model) 8
1.3 雜訊對神經訊號傳遞之影響 9
1.4 雜訊對神經電路模型之影響 9
第二章 文獻探討 11
2.1 低頻雜訊元件 11
2.2 淺溝槽隔離型場效電晶體(Shallow-trench-isolation field-effect transistor, STIFET) 12
2.2.1 淺溝槽隔離製程(Shallow-trench-isolation) 13
2.2.2 原生遮罩(Native Mask) 14
2.2.3 STIFET構造 14
2.2.4 STIFET雜訊特性 15
2.3 八邊型雙閘極場效電晶體(Octagonal dual-gate field-effect transistor, ODGFET) 17
2.3.1 ODGFET構造 17
2.3.2 ODGFET雜訊特性 18
2.4 電阻保護氧化層場效電晶體(Resist-protection-oxide field-effect transistor, RPOFET) 19
2.4.1 電阻保護氧化層製程 20
2.4.2 RPOFET構造 21
2.4.3 RPOFET雜訊特性 22
2.5 討論 24
第三章 STIFET簡介及量測結果 25
3.1 STIFET結構 25
3.2 量測結果 26
3.3 討論 29
第四章 STIFET模型建立 30
4.1 長通道STIFET模型 30
4.2 短通道STIFET模型 34
4.2.1 以ID-VGS 關係圖模擬 34
4.2.2 以ID-VDS 關係圖模擬 39
4.2.3 在不同源極電壓下之短通道STIFET模型 43
4.3 模擬結果 45
4.3.1 長通道STIFET模擬結果 45
4.3.2 短通道STIFET模擬結果 47
4.3.3 考量源極電壓變化之短通道STIFET模擬結果 50
4.4 討論 52
第五章 ODGFET模型建立 54
5.1 ODGFET結構 54
5.2 量測結果 55
5.3 ODGFET模型 57
5.4 模擬結果 62
5.5 討論 67
第六章 RPOFET模型建立 68
6.1 RPOFET結構 68
6.2 量測結果 70
6.3 RPOFET模型與模擬結果 71
6.3.1 雙原生電晶體模型 71
6.3.2 原生電晶體-STIFET串聯模型 77
6.3.3 原生電晶體-電阻串聯模型 79
6.4 討論 81
第七章 結論 84
參考資料 86
附錄 88
A 短通道STIFET模擬結果 88
B 短通道STIFET不同源極電壓之模擬結果 94
C ODGFET模擬結果 102

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