隨著電晶體製程依據摩爾定律不斷的演進，我們必須面對設計上的困難以及物理上的瓶頸，其中包含漏電流的增加、跑線的延遲與能量消耗以及生產良率的問題。目前最有潛力解決上述問題並且能有效增加密度以及效能的方法為三維晶片堆疊整合。三維晶片堆疊整合使用直通矽穿孔(Through Silicon Via,TSV)技術使得不同的晶片可以三維方式堆疊整合，但目前TSV技術仍有許多挑戰，包含直通矽穿孔的負載過重、製程變異過大導致效能不佳、直通矽穿孔的面積過大使得面積效益不彰、多層晶片的定址問題以及傳輸效率提升與頻寬之效能問題等等。於這些三維堆疊製程整合的重要議題中，本論文探討如何藉由電路設計減少三維傳輸的能量消耗、以提高傳輸效能以及合適的傳輸界面。
因此，在論文中我們提出了具非對稱性感測放大器之資料警覺低電壓電荷共享傳輸方案。其中資料警覺低電壓電荷共享傳輸方案能夠有效節省高負載TSV傳輸所消耗的能量，能夠依據傳輸的資料動態調整TSV上的電荷，以減少對TSV充電的量值，且在多層堆疊時能夠有效降低傳輸速度的損失。而非對稱性感測放大器可以解決傳統對稱型感測放大器所面臨參考點電壓選擇的問題，並且能降低感測資料所需的最小資料端電壓差距。
我們使用六十五奈米互補金氧半導體技術來設計一個由一千零二十四組傳輸電路組成的三維堆疊傳輸方案來驗證我們的想法，量測結果顯示傳輸效能可達到0.12 mW/Gbps。

With the evolution of MOS technology based on Moore’s Law, we have to face the difficulties on designing and the bottleneck on physics and materials including increasing leakage current, RC delays on wire routing and yield issue. 3D integration has the most potential to solve these problems by using Though Silicon Via (TSV) technology and providing outstanding performance and high density advantage at the same time. However, there are many challenges for TSV-based 3D IC such as bad energy efficiency due to large loading, multi layer addressing and large TSV pitch. Therefore, the capability of achieving low energy efficiency by circuit design for 3D IC is the main target of our works. In the thesis, we propose a Data-Aware Charge-Sharing Low Voltage Transmission Scheme with Asymmetric Sense Amplifier to reduce the power consumption and solve the Vref selecting problems for conventional symmetric sense amplifier. A 1kb I/O macro has been fabricated in 65nm CMOS technology to verify the ideas of this works. The measurement results demonstrate the functionality of this works and the energy efficiency can achieve to 0.12 mw/Gbps.

ontent
摘要 I
ABSTRACT II
LISTS OF FIGURES VI
LISTS OF TABLES VIII
ACRONYMS IX
CHAPTER 1. INTRODUCTION 1
1.1 MOTIVATION AND APPLICATION FOR 3D IC 1
1.2 FEATURES OF 3D IC 4
1.3 EMERGING TECHNOLOGY: 3D-IC 5
1.3.1 Die/Wafer Assembly 5
1.3.2 3D Stacking Styles 6
1.3.3 TSV Process 7
1.4 THESIS ORGANIZATION 8
CHAPTER 2. CHARACTERISTIC AND ANALYSIS OF ITRI’S 3D IC PROCESS 9
2.1 INTRODUCTION TO ITRI 3D IC PROCESS 9
2.2 RC CHARACTERISTIC ANALYSIS FOR ITRI 3D PROCESS 10
CHAPTER 3. DESIGN CHALLENGES FOR 3D IC 13
3.1 DESIGN CHALLENGES 13
3.1.1 Power and Speed Tradeoff 13
3.1.2 Signal Skew 14
3.1.3 TSV Yield 16
3.2 PREVIOUS WORKS 17
3.2.1 A Compact Low Power 3D I/O 17
3.2.2 Low Swing I/O with Pre-emphasis Tx 18
3.2.3 Process Calibration Scheme for Timing Skew 19
3.2.1 TSV Defect Detect and Repair Scheme in 3D IC 21
3.3 CONCEPTS OF PROPOSED 3D IC TRANSMISSION SCHEME 23
3.3.1 Analysis of Energy Distribution In 3D Transient 23
3.3.2 Concepts of Proposed Works 24
3.3.3 Introduction of Symmetric Sense-Amplifier 25
CHAPTER 4. PROPOSED 3D IC TRANSMISSION SCHEME 27
4.1 DATA-AWARE LOW VOLTAGE CHARGE-SHARING SCHEME 27
4.1.1 Low Voltage Transmission 27
4.1.2 Data-aware Charge-Sharing Scheme 28
4.2 ASYMMETRIC SENSE-AMPLIFIER 31
4.2.1 Reference Voltage Fixation 32
4.2.2 Proposed Asymmetric Sense-Amplifier operation 35
4.3 PIPELINED TIMING STRUCTURE 36
CHAPTER 5. ANALYSIS AND COMPARISONS 39
5.1 ANALYSIS OF DATA-AWARE CHARGE-SHARING SCHEME 39
5.1.1 Data Pattern Analysis 39
5.1.2 Energy Analysis 41
5.1.3 Peak Current Analysis on TSV loading 44
5.2 ANALYSIS OF ASYMMETRIC SENSE AMPLIFIER 45
5.2.1 Sense Amplifier Offset Analysis 46
5.3 ANALYSIS OF PROPOSED TRANSMISSION SCHEME 47
5.4 STRUCTURE COMPARISONS 47
CHAPTER 6. CHIP IMPLEMENTATION 49
6.1 ARCHITECTURE OF PROPOSED I/O MACRO 49
6.1.1 Unit I/O Cell 49
6.1.2 Block Diagram of the Proposed I/O Macro 50
6.2 ARCHITECTURE FOR MULTI-LAYER OPERATION 52
6.3 TEST CHIP DESIGN 53
CHAPTER 7. MEASUREMENT RESULTS AND CONCLUSIONS 55
7.1 MEASUREMENT RESULTS 55
7.2 CONCLUSIONS OF PROPOSED SCHEME 60
7.3 FUTURE WORK 62
REFERENCES 63

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