現今的半導體記憶體種類繁雜，反及閘型快閃記憶體卻有著其重要的角色扮演。由於其陣列的排列方式，反及閘型快閃記憶體可以達到極高的密度，這在當今可攜式電子產品蓬勃發展、大量資料存取應用中，是有著不可取代且重要的設計考量。並且因為其容量大，因此佔整個晶片非常大的面積，如果可以降低反及閘型快閃記憶體的製造成本，即可大幅增加競爭力。
在目前的系統應用晶片中，內嵌式的反及閘型快閃記憶體需要高電壓使電子進入懸浮閘極來完成〝寫入〞的機制，而電荷幫浦則普遍地用在晶片內部以產生一個比供應電源更高的正電壓或比零更低的負電壓。然而，因為電荷幫浦產生的高電壓會有〝漣漪〞的現象，會在目標電壓上下的震動，造成反及閘型快閃記憶體在〝寫入〞機制時的垂直電場強度改變，影響到反及閘型快閃記憶體〝寫入〞的電子數量，因此對記憶體元件來說，邏輯1和邏輯0的差異性會變小，或者是，造成〝寫入〞程度不準的問題，進而造成記憶體資料存取錯誤。
我們提出一電荷幫浦輸出偵測機制，當輸出電壓的漣漪電壓大到某個程度時，會經由一回授電路來降低電荷幫補的幫浦能力，這樣既能保持電荷幫浦原來的啟動時間，亦能降低穩態時的電荷幫浦的漣漪電壓。

指導教授推薦書 ii
口試委員審定書 iii
摘要 iv
Abstract v
致謝 vi
List of Figure x
第一章 簡介 1
1.1 反及閘型快閃記憶體的介紹 1
1.2 高密度反及閘型快閃記憶體的挑戰 4
1.3 論文概述 7
第二章 三維反及閘型快閃記憶體的介紹 8
2.1 Bandgap Engineered Silicon-Oxide-Nitride- Oxide-Silicon (BE-SONOS)記憶體元件 8
2.2 陣列組織 11
2.3 讀取操作 13
2.4 寫入操作 15
2.4.1 寫入 15
2.4.2 自我升壓抑制寫入機制 (Self-Boost Program Inhibit, SBPI) 16
2.4.3 寫入驗證機制 19
2.4.4 階層增量脈衝寫入 (Incremental Step Pulse Programming, ISPP) 21
2.5 抹除操作 22
2.5.1 電洞穿隧抹除 22
2.5.2 自我升壓抑制抹除機制 (Self-Boost Erase Inhibit, SBEI) 23
2.5.3 抹除驗證機制 25
第三章 三維垂直閘反及閘型快閃記憶體(3DVG NAND)挑戰 28
3.1 位元線的耦合雜訊 28
3.2 共用資源線的雜訊 32
3.3 各層間臨界電壓需求 34
3.4 背景資料相關聯影響 (Background Pattern Dependency, BPD) 36
3.5 電荷幫浦漣漪電壓雜訊 (Charge Pump Ripple Noise) 38
第四章 電荷幫浦在快閃記憶體中的應用 39
4.1 切換式電容電荷幫浦 39
4.2 切換式電容電荷幫浦電路實現 41
4.3 交叉耦合式倍壓器 (Cross-Coupled Structure) 42
4.4 交叉耦合式電荷幫浦升壓電路 44
4.5 電荷幫浦系統 45
4.6 反及閘型快閃記憶體中的電荷幫浦系統 47
第五章 提出的架構與操作方式 50
5.1 電荷幫浦升壓起始時間與漣漪電壓的關係 50
5.2 提出的快速啟動與小漣漪電壓的電荷幫浦系統 51
5.2.1 電荷幫浦分支關閉機制 51
5.2.2 電荷幫浦時脈拆碎調控 55
第六章 分析與比較 57
6.1 傳統降低漣漪電壓的作法 57
6.2 模擬條件 58
6.3 模擬結果 59
第七章 晶片實現 62
7.1 測試晶片架構 62
7.2 晶片實作照片 & layout 63
7.3 Printed Circuit Board(PCB)實作 65
7.4 量測結果 66
第八章 結論與未來的研究 68
Reference 69

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