手持性消費電子產品、醫療電子、車用電子等大量電子產品對非揮發性記憶體的需求愈來愈大，尤其是大容量、低成本、低耗能和高速度的記憶體，和微控制單元(MCU)整合之後可以有效地提升晶片的效能。目前常見的快閃記憶體(NAND Flash Memory)其寫入速度慢且無法隨機存取，隨著製成衍進成奈米等級之後，快閃記憶體在微縮尺寸上面遇到了困難，因此有其必要開發新型的非揮發性記憶體。而電阻式記憶體(ReRAM)是相當具有潛力的非揮發性記憶體，其特色為低寫入功耗、小面積、以及具有邏輯製成相容性，可降低製作成本。
目前普遍的ReRAM記憶細胞架構為一個電晶體和一個ReRAM的組合(1T1R)，適合用在需要快速讀取和低供給電壓的內嵌式裝置應用上，特別是電池供給的裝置。隨著元件的微縮，ReRAM的阻值愈來愈高，且寫入時間和阻值的飄移量愈來愈大，造成高阻態和低阻態之間的R-ratio(RH/RL)縮小。除此之外，ReRAM的低阻態偏高，有助於增加寫入時跨在ReRAM上面的跨壓，如此一來，可以減少寫入的電壓，以及記憶細胞架構電晶體的大小。
因此ReRAM記憶體會面臨到兩個問題：
1. 因為ReRAM的低阻態偏高，且R-ratio變小，使得讀取的感測範圍
(sensing margin)變小，進而造成讀取速度慢，並限制了記憶體的最低操作電壓。
2. 由於寫入時間的漂移，大寫入電流(IDC-SET)會造成大量的能量消耗。
在此，我們提出兩個電路來解決上述遇到的兩種問題，分別是swing-sample-and-couple voltage mode sense amplifier (SSC-VSA)和self-boost-write-termination (SBWT) scheme。
我們所提出的SSC-VSA把參考電壓設計在特別的準位上面，經由電路運作後，能夠有效率的把ΔVBLS_MIN當作讀取感測範圍，使得使用率高達99%，因此能操作在更低的電壓以及擁有更快的讀取速度，其讀取速度可比傳統的電壓感測電路快1.7倍以上。
至於ReRAM的寫入方面，我們提出SBWT scheme，它是一個4T的自動偵測寫入完成電路，當ReRAM set (HRS→LRS)成功時，大寫入電流會使得BL電壓上升，啟動BL和SBWT之間的正向回饋機制，切斷電流路徑，可節省99%以上的耗能。
我們以28奈米製程實作1Mb ReRAM記憶體晶片，在供給電壓等於0.85V及0.27V下，量測讀取速度分別為6.8ns和404.4ns。除此之外，我們也成功驗證寫入終止電路機制。

The requirements of non-volatile memories for handheld consumer electronics, medical electronics, car electronics, and lots of electronic products become larger and larger, especially for large capacity, low cost, low power and high speed memory. After integrated with micro controller unit (MCU), it can effectively increase the chip performance. Flash memory is the mainstream embedded memory. However, it cannot achieve high speed write operation and be randomly accessed. Furthermore, it is difficult to scale down flash memory into deep nanometer scale. Thus, developing new nonvolatile memories is necessary. Among these emerging nonvolatile memories, Resistive Random Access Memory (ReRAM) is one of the most promising candidates. It has attractive characteristics such as low write power, small area, and logic-process compatibility which can lower the manufacturing cost.
Currently, the most common memory cell structure is one transistor and one ReRAM (1T1R), which is suitable for high speed and low supply voltage embedded applications, particularly for devices powered by batteries. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (RH/RL) between the high-R state (HRS, RH) and low-R state (LRS, RL). ReRAM also has a high RL, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size.
Thus, ReRAM memory macro designs suffer two major problems：
1. Small sensing margin (SM), limited read-VDDMIN, and slow access time (TAC) due
to high-RL and small R-ratio.
2. Increase in energy due to large set DC-current (IDC-SET) resulting from wide set-time
(TSET) distribution.
Here, we propose swing-sample-and-couple voltage mode sense amplifier (SSC-VSA) and self-boost-write-termination (SBWT) scheme to solve above two major problems, respectively.
Proposed SSC-VSA designs the VREF on specific voltage level, after the operation of the circuit, it can increase the usage of ΔVBLS_MIN (by up to 99%) as the SM for lower read VDDMIN and faster TAC. It can achieve 1.7x faster TAC across various VDD compared to conventional differential-input (CD) voltage mode sense amplifier.
As for ReRAM write operation, proposed SBWT scheme is a 4T self-detective write-termination circuit. When ReRAM successfully sets (HRS→LRS), large IDC-SET will increase the BL voltage, enabling the positive feedback between BL and SBWT and cutting off the current path, which can save over 99% write power.
We fabricated a 28nm 1Mb ReRAM memory macro. Under the 0.85V and 0.27V supply voltage, the measured read access times are 6.8ns and 404.4ns, respectively. Besides, the SBWT scheme has also been demonstrated.

國家圖書館博碩士紙本論文延後公開/下架申請書 i
指導教授推薦書 ii
口試委員審定書 iii
摘要 iv
Abstract vi
致謝 viii
Contents x
List of Figures xiii
List of Tables xvi
Chapter 1 Introduction 1
1.1 The Memory Landscape 1
1.2 Challenges of Flash Memory 2
1.3 Emerging Non-Volatile Memories 4
1.4 Applications of Low Power ReRAM 7
Chapter 2 Characteristics of Contact-ReRAM [43] 11
2.1 Structure of Contact-ReRAM 11
2.2 Switching Mechanism 12
2.3 Write Operation 13
2.4 Read Operation 14
2.5 Distribution of Contact-ReRAM 15
Chapter 3 Design Challenges of Low Power ReRAM 17
3.1 Sense Amplifier 17
3.1.1 ReRAM Read Issue 17
3.1.2 Conventional Sensing Scheme 19
3.1.3 Previous Work 20
3.2 Write Circuit 24
3.2.1 Conventional Write Scheme 24
3.2.2 Previous Work 25
Chapter 4 Proposed Circuits Schemes 27
4.1 Swing-Sample-and-Couple Voltage Mode Sense Amplifier (SSC-VSA) 27
4.1.1 Concept of Proposed Sensing Scheme 27
4.1.2 Operation of Proposed SSC-VSA 28
4.1.3 VREF Generation of Proposed SSC-VSA 31
4.2 Self-Boost-Write-Termination Scheme (SBWT Scheme) 33
4.2.1 Concept of Proposed Write Termination Scheme 33
4.2.2 Operation of Proposed SBWT Writer Driver 34
Chapter 5 Analyses and Comparisons 36
5.1 Proposed SSC-VSA 36
5.1.1 Sensing Margin Comparison 36
5.1.2 Speed Comparison 38
5.1.3 Analyses of the Capacitor in SSC-VSA 39
5.2 Proposed SBWT-WD 40
Chapter 6 Macro Implementation 43
6.1 CRRAM Macro 43
6.2 Design for Timing Control 45
6.3 Design for Low Voltage Application 46
6.4 Design for Test Chip 47
Chapter 7 Experimental Result and Conclusion 49
7.1 Performance Measurement 50
7.2 Conclusions and Future Work 52
Reference 56

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