隨著科技的進步，現代人對於優質的生活環境及健康的身體狀況，其需求有增加的趨勢。醫療照護、營養的攝取與公共衛生等技術的進步，使社會逐漸轉型為高齡化社會，健康照護的需求或者是慢性病所需要長時間紀錄並且能夠即時地監控人體各種生醫訊號的醫療儀器設備的需求日益增加。而腦波訊號是反映人體生理指數的重要指標之一，臨床醫療上常有連續式腦電波量測的長時間監測與紀錄的需求，如癲癇、阿茲罕默症、憂鬱症與精神分裂疾病，皆屬於患者的偶發性腦波不正常放電。近幾年的研究中，愈來愈多的文獻投入在研究人體各類生理訊號的特性以及其應用的擷取系統電路，並且將積體電路晶片整合成適用於長時間監測與擁有可攜式特性的裝置。在這類裝置中，避免雜訊干擾，進而把將感測到的微弱生理訊號加以放大，即為最前端的低雜訊前端生醫放大器。
本篇研究為針對擷取腦波訊號設計的可程式化增益之多通道低雜訊前端擷取電路，低雜訊生醫訊號前端電路採用擁有全差動儀表放大器做為低雜訊的第一級核心放大器設計，電晶體在低頻時受到閃爍雜訊影響相當嚴重，進一步使用截波穩定技術輔助我們有效地減少電路中的閃爍雜訊，而截波穩定放大器下一級採用低轉導電容濾波器來濾除我們感興趣頻帶以外的雜訊，為了避免輸出訊號飽和利用可調增益放大器來調整適當的輸出訊號振幅，最後透過類比數位轉換器將擷取到的訊號轉換成數位碼送至後端數位訊號處理做數據紀錄與分析。本篇研究使用TSMC 90nm CMOS 標準製程實現。在0.5 V供應電壓下整體系統電路總功率消耗為29.08 μW。低雜訊生醫訊號前端電路在EEG的頻寬範圍內，其輸入總等效雜訊為0.358 μVrms，NEF為2.43，PEF為2.95，共模互斥比為91.9 dB，其模擬結果顯示此電路適用於腦波訊號之生醫訊號擷取系統。

Abstract
In recent years, bio-medical electronics have been developed rapidly, especially the application of portable bio-potential signal acquisition. The bio-potential signals most commonly used in medical diagnoses include EEG, ECG and EMG, etc. However, the recordings of these signals are inconvenient and uncomfortable for patients, because they need to be connected to a stationary and bulky instrument during the examination. Moreover, the bio-potential signals reflect the physiological status of patients. In order to acquire the physiological information from patients effectively, recording multi-point at the same time is important. Therefore, there are growing demands for small size and multi-channel bio-potential signal acquisition system to improve the patients’ quality of daily life.
This article presents a programmable low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential chopper instrumentation amplifiers each with a small Gm-C low-pass filter, a programmable gain amplifier. The chip is fabricated with the TSMC 90nm CMOS process. The analog readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, a power efficiency factor (PEF) of 2.95. The overall system consumes 29.08 µW under 0.5-V supply.

目錄
中文摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 viii
表目錄 xii
第1章 緒論 1
1.1 研究背景 1
1.2 相關研究發展 2
1.2.1 非植入式生醫訊號擷取裝置系統介紹 2
1.2.2 生醫訊號簡介 3
1.2.3 生醫訊號感測電極 5
1.3 系統設計規格需求 9
1.4 章節簡介 11
第2章 文獻回顧 12
2.1 低雜訊生醫訊號放大器 12
2.1.1 電阻回授式儀表放大器 12
2.1.2 電容回授式儀表放大器 13
2.1.3 差動差分放大器 15
2.1.4 電流平衡式儀表放大器 16
2.2 動態開關雜訊消除技術 17
2.2.1 截波穩定技術 (Chopper Stabilization Technique) 17
2.2.2 自動歸零技術 (Auto-Zeroing Technique) 20
第3章 雜訊 22
3.1 雜訊簡介 22
3.2 低雜訊放大器雜訊 23
3.2.1 熱雜訊 (Thermal Noise) 23
3.2.2 閃爍雜訊 (Flicker Noise) 25
3.2.3 散射雜訊 (Shot Noise) 28
3.2.4 隨機電報訊號雜訊 (Random Telegraph Signal Noise, RTS) 28
3.2.5 產生復合雜訊 (Generation-Recombination Noise, G-R Noise) 29
3.2.6 電磁干擾(EMI)與靜電場干擾(EFI) 30
3.3 低雜訊放大器雜訊設計考量 31
3.3.1 低雜訊放大器設計分析工具 31
3.4 雜訊與功率效能指數 34
3.4.1 雜訊效能指數 (Noise Efficiency Factor, NEF) 34
3.4.2 功率效能指數 (Power Efficiency Factor, PEF) 35
第4章 低雜訊生醫訊號前端電路系統架構與設計流程 36
4.1 整體系統架構簡介 36
4.2 低雜訊生醫訊號前端電路 36
4.2.1 截波穩定技術 (Chopper Stabilization Technique) 37
4.2.2 低雜訊儀表放大器 40
4.2.3 低轉導電容之低通濾波器 48
4.2.4 可程式化調變增益放大器 51
4.2.5 共模回授電路 55
第5章 電路模擬與佈局 57
5.1 Pre-Simulation 57
5.1.1 截波穩定儀表放大器模擬 57
5.1.2 低轉導值電容濾波器模擬 59
5.1.3 生醫訊號低雜訊前端電路模擬 59
5.2 電路佈局與考量 62
5.3 Post-Simulation 63
5.3.1 截波穩定儀表放大器模擬 64
5.3.2 低轉導值電容濾波器模擬 66
5.3.3 生醫訊號前端電路模擬 66
第6章 量測結果分析與討論 71
6.1 量測設置 71
6.2 生醫訊號前端電路 73
6.2.1 雜訊 73
6.2.2 頻率響應 75
6.2.3 暫態響應 77
6.2.4 儀表放大器共模拒斥比 82
6.2.5 低雜訊生醫訊號前端電路量測結果 83
6.3 文獻比較表 84
6.4 量測結果討論 85
第7章 結論與未來展望 90
7.1 結論 90
7.2 未來展望 90
參考文獻 91

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