本論文提出一個低電壓操作，且高能源效率的混合式類比數位轉換器(ADC)，應用於儀器量測校準與生醫的領域上。基於混和式ADC的架構與技巧，在系統上我們分別在前端使用了六位元解析度的連續逼近暫存類比數位轉換器(SAR ADC)，以及在後端使用了增量形三角積分轉換器(Incremental Sigma-Delta Modulator)，進一步達到了整體所預計的解析度。
為了降低整體電路的功耗，我們針對前端SAR ADC的電容切法做了改善與創新，成功降低了所需的switching energy。而在後端的Incremental Sigma-Delta Modulator，使用了切換式運算放大器技術來解決小於一伏特低電壓下MOS開關無法傳遞訊號之問題，也藉由Cascade-of-Integrators Feed-forward (CIFF) 架構將輸入訊號直接向前傳遞至量化器輸入端使得各級積分器內的訊號擺幅減小，藉此減少在低電壓下運算放大器的規格要求。再者，SAR ADC中的電容陣列是以unary的方式做實現，意即每個電容都是單位電容，再配合上Dynamic Element Matching(DEM)，將存在電容陣列上的誤差打散，得到更好的線性度，進一步達到系統所需的規格。
此架構使用TN90GUTM 1P9M 互補式金氧半導體製程製作，晶片面積為0.301mm2。在512-kHz的取樣頻率以及0.5-ms的conversion time下，達到了整體92.66-dB的SNDR，並且在500-mV的操作電壓下消耗了5.481μW，等效所得到的figure of merit(FoM) 為175.93-dB，和其他的成果相比較也是具有競爭力的。

This Thesis presents a low-voltage operation and high energy efficient hybrid analog-to-digital converter (ADC) for instrumentation or biomedical systems applications. It is based on an energy-efficient hybrid ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine incremental ΔΣ conversion, to achieve target resolution performance.
The proposed ADC operates at ultra-low supply voltage, 0.5V, to save power consumption. Novel switching technique in coarse SAR ADC is utilized to improve the power efficiency of the ADC in low voltage operation. In fine incremental ΔΣ modulator, switched-op amp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of integrators feed-forward (CIFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. Furthermore, SAR ADC comprises a 6 bit unary-weighted capacitor DAC array, which means every capacitor in the DAC array is equal to unit capacitor. Dynamic element matching (DEM) is used to average the mismatch and error on capacitor DAC array, hence achieve both low offset and high linearity.
The proposed ADC is fabricated in TN90GUTM technology, achieving a 92.66-dB SNDR at 512-kHz sampling rate and 0.5-ms conversion time. The proposed ADC occupies core area of 0.301-mm2 and dissipates only 5.481-μW from a 500-mV power supply. The figure of merit (FoM) of overall ADC is 175.93-dB, which is competitive to state-of-the-art designs.

ABSTRACT II
CONTENTS IV
LIST OF FIGURES VIII
LIST OF TABLES XI
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS CONTRIBUTION 3
1.3 THESIS ORGANIZATION 4
CHAPTER 2 BACKGROUND INFORMATION 6
2.1 ARCHITECTURE SELECTION 7
2.2 PERFORMANCE METRICS OF ADC 8
2.2.1 Resolution 8
2.2.2 Signal-to-Noise Ratio (SNR) 9
2.2.3 Quantization Error 9
2.2.4 Oversampling / Nyquist-Rate ADC 9
2.2.5 Effective Number of Bit (ENOB) 10
2.2.6 Differential Nonlinearity (DNL) 10
2.2.7 Integral Nonlinearity (INL) 10
2.2.8 Figure of Merit (FOM) 11
2.3 PROTOTYPE OF SAR ADC 11
2.3.1 Conventional Single-Ended SAR ADC 11
2.3.2 Conventional Differential SAR ADC 13
2.4 PROTOTYPE OF INCREMENTAL SIGMA DELTA MODULATOR 15
2.4.1 Operation Principle 16
2.4.2 Design Methodology 18
2.5 SUMMARY 19
CHAPTER 3 CIRCUIT-LEVEL DESIGN CONSIDERATION 20
3.1 CDAC SWITCHING ENERGY 20
3.1.1 Conventional DAC Switching 20
3.1.2 Vcm-Based DAC Switching 23
3.1.3 Monotonic DAC Switching 25
3.1.4 Switchback DAC Switching 28
3.1.5 Charge Average DAC Switching 30
3.1.6 Shifted Monotonic DAC Switching 33
3.2 SAMPLE AND HOLD DESIGN CONSIDERATION 35
3.3 COMPARATOR DESIGN CONSIDERATION 35
3.4 DIGITAL SAR CONTROL DESIGN CONSIDERATION 37
3.5 DYNAMIC ELEMENT MATCHING (DEM) CONSIDERATION 37
3.6 OP AMP DESIGN CONSIDERATION 38
3.6.1 Thermal Noise and Flicker Noise 39
3.6.2 Finite Gain and GBW 41
3.6.3 Settling Error 42
3.7 TWO-STEP ADC DESIGN CONSIDERATION 43
3.8 SUMMARY 44
CHAPTER 4 PROPOSED ARCHITECTURE IMPLEMENTATION 45
4.1 PROPOSED ADC ARCHITECTURE 45
4.1.1 Coarse SAR ADC 45
4.1.2 Fine Incremental ΣΔ Modulator 47
4.2 SAMPLE AND HOLD DESIGN 49
4.3 DYNAMIC COMPARATOR DESIGN 50
4.4 DIGITAL SAR CONTROL LOGIC DESIGN 50
4.5 DYNAMIC ELEMENT MATCHING DESIGN 51
4.6 OPAMP DESIGN 52
4.7 OTHER SUB-CIRCUITS 53
4.7.1 Non-overlapping Clock Generator 53
4.7.2 SR Latch 54
4.7.3 Decimation Filter 54
4.8 PRE-LAYOUT AND POST-LAYOUT SIMULATION RESULTS 55
4.8.1 Op Amp Simulations 56
4.8.2 Coarse SAR Simulations 56
4.8.3 Fine I-ΣΔ Simulations 57
4.8.4 DAC mismatch and DEM function 58
4.8.5 Proposed ADC Simulations 58
4.9 SUMMARY 60
CHAPTER 5 CHIP IMPLEMENTATION AND MEASUREMENT 60
5.1 CHIP IMPLEMENTATION 61
5.2 MEASUREMENT ENVIRONMENT SETUP 62
5.3 MEASUREMENT RESULTS 64
5.4 PERFORMANCE SUMMARY AND COMPARISON 69
5.5 SUMMARY 71
CHAPTER 6 CONCLUSIONS 72
6.1 SUMMARY 72
6.2 FUTURE WORK 73
BIBLIOGRAPHY 75

[1] J. Goes, N. Paulino, H. Pinto, R. Monteiro, B. Vaz, and A. S. Garcao, “Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12, pp. 2595- 2604, Dec. 2005.
[2] J. Johansson, H. Neubauer, and H. Hauer, “A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications,” in Proc. Eur. Solid-State Circuit Conf., pp. 161-164, Sept. 2003.
[3] S.-Y. Lee, and C.-J. Cheng, “A Low-Voltage and Low-Power Adaptive Switched-Current Sigma-Delta ADC for Bio-Acquisition Microsystems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2628-2636, Dec. 2006.
[4] J. Xu, X. Wu, H. Wang, J. Shen, and B. Liu, “Power optimization of high performance ΔΣ modulators for portable measurement applications,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), pp.1-4, Nov. 2010.
[5] F. Cannillo, E. Prefasi, L. Hernandez, E. Pun, F. Yazicioglu, and C. V. Hoof, “1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. Eur. Solid-State Circuit Conf., pp. 267-270, Sept. 2011.
[6] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585-1593, July 2012.
[7] Youngcheol Chae; Souri, K.; Makinwa, K.A.A., "A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset," in Solid-State Circuits, IEEE Journal of , vol.48, no.12, pp.3019-3027, Dec. 2013
[8] Thomsen, A.; de Angel, E.; Wu, S.X.; Amar, A.; Lei Wang; Wai Lee, "A DC measurement IC with 130 nVpp noise in 10 Hz," in Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International , vol., no., pp.334-335, 9-9 Feb. 2000
[9] Quiquempoix, V.; Deval, P.; Barreto, A.; Bellini, G.; Markus, J.; Silva, J.; Temes, G.C., "A low-power 22-bit incremental ADC," in Solid-State Circuits, IEEE Journal of , vol.41, no.7, pp.1562-1571, July 2006
[10] Rong Wu; Youngcheol Chae; Huijsing, J.H.; Makinwa, K.A.A., "A 20-b ±40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers," in Solid-State Circuits, IEEE Journal of , vol.47, no.9, pp.2152-2163, Sept. 2012
[11] Harpe, P.; Cantatore, E.; van Roermund, A., "A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step," in Solid-State Circuits, IEEE Journal of, vol.48, no.12, pp.3011-3018, Dec. 2013
[12] Chang-Yuan Liou; Chih-Cheng Hsieh, "A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International , vol., no., pp.280-281, 17-21 Feb. 2013
[13] Hurrell, C.P.; Lyden, C.; Laing, D.; Hummerston, D.; Vickery, M., "An 18 b 12.5 MS/s ADC With 93 dB SNR," in Solid-State Circuits, IEEE Journal of , vol.45, no.12, pp.2647-2654, Dec. 2010
[14] Zhichao Tan; Daamen, R.; Humbert, A.; Ponomarev, Y.V.; Youngcheol Chae; Pertijs, M.A.P., "A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications," in Solid-State Circuits, IEEE Journal of , vol.48, no.10, pp.2469-2477, Oct. 2013
[15] Markus, J.; Silva, J.; Temes, G.C., "Theory and applications of incremental ΔΣ converters," in Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.51, no.4, pp.678-690, April 2004
[16] Bonizzoni, E.; Perez, A.P.; Caracciolo, H.; Stoppa, D.; Maloberti, F., "An incremental ADC sensor interface with input switch-Less integrator featuring 220-nVrms resolution with ±30-mV input range," inESSCIRC (ESSCIRC), 2012 Proceedings of the , vol., no., pp.389-392, 17-21 Sept. 2012
[17] Nys, O.J.A.P.; Dijkstra, E., "On configurable oversampled A/D converters," in Solid-State Circuits, IEEE Journal of , vol.28, no.7, pp.736-742, Jul 1993
[18] Yao Liu; Bonizzoni, E.; D'Amato, A.; Maloberti, F., "A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply," in ESSCIRC (ESSCIRC), 2013 Proceedings of the , vol., no., pp.371-374, 16-20 Sept. 2013
[19] Rombouts, P.; De Wilde, W.; Weyten, L., "A 13.5-b 1.2-V micropower extended counting A/D converter," in Solid-State Circuits, IEEE Journal of , vol.36, no.2, pp.176-183, Feb 2001
[20] Agah, A.; Vleugels, K.; Griffin, Peter B.; Ronaghi, M.; Plummer, James D.; Wooley, B.A., "A High-Resolution Low-Power Oversampling ADC with Extended-Range for Bio-Sensor Arrays," in VLSI Circuits, 2007 IEEE Symposium on , vol., no., pp.244-245, 14-16 June 2007
[21] Cook, B.W.; Lanzisera, S.; Pister, K.S.J., "SoC Issues for RF Smart Dust," in Proceedings of the IEEE , vol.94, no.6, pp.1177-1196, June 2006
[22] Anantha P. Chandrakasan, Naveen Verma, and Denis C. Daly, "Ultralow-Power Electronics for Biomedical Applications," Annual Review of Biomedical Engineering, Vol. 10: 247-274
[23] B. Murmann, “ADC Performance Survey 1997-2013,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
[24] de la Rosa, J.M., "Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey," in Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.58, no.1, pp.1-21, Jan. 2011
[25] R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation 2/e”, John Wiley, 2006.
[26] McCreary, J.L.; Gray, P.R., "All-MOS charge redistribution analog-to-digital conversion techniques. I," in Solid-State Circuits, IEEE Journal of , vol.10, no.6, pp.371-379, Dec. 1975
[27] Hester, R.K.; Tan, K.-S.; De Wit, M.; Fattaruso, J.W.; Kiriaki, S.; Hellums, J.R., "Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation," in Solid-State Circuits, IEEE Journal of , vol.25, no.1, pp.173-183, Feb 1990
[28] R. Schreier. (2003) The Delta–Sigma toolbox v6.0 (Delsig). Mathworks, Natick, MA.[Online].Available: http://www.mathworks.com/matlabcentral/fileexchange/
[29] Yan Zhu; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U; Martins, R.P.; Maloberti, F., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," in Solid-State Circuits, IEEE Journal of , vol.45, no.6, pp.1111-1121, June 2010
[30] Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in Solid-State Circuits, IEEE Journal of , vol.45, no.4, pp.731-740, April 2010
[31] Guan-Ying Huang; Soon-Jyh Chang; Chun-Cheng Liu; Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.21, no.3, pp.584-588, March 2013
[32] Sung-En Hsieh, and Chih-Cheng Hsieh, “A 0.3V 0.705fJ/Conversion-step 10-bit SAR ADC with Shifted Monotonic Switching Procedure in 90nm CMOS,” in IEEE International symposium on circuits and systems, in press.
[33] Guan-Ying Huang; Chun-Cheng Liu; Ying-Zu Lin; Soon-Jyh Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," in Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian , vol., no., pp.157-160, 16-18 Nov. 2009
[34] Harpe, P.; Zhou, C.; Xiaoyan Wang; Dolmans, G.; de Groot, H., "A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios," in ESSCIRC, 2010 Proceedings of the , vol., no., pp.214-217, 14-16 Sept. 2010
[35] Harpe, P.; Busze, B.; Philips, K.; de Groot, H., "A 0.47–1.6mW 5bit 0.5–1GS/s time-interleaved SAR ADC for low-power UWB radios," in ESSCIRC (ESSCIRC), 2011 Proceedings of the , vol., no., pp.147-150, 12-16 Sept. 2011
[36] Harpe, P.J.A.; Zhou, C.; Yu Bi; van der Meijs, N.P.; Xiaoyan Wang; Philips, K.; Dolmans, G.; de Groot, H., "A 26 μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," in Solid-State Circuits, IEEE Journal of , vol.46, no.7, pp.1585-1595, July 2011
[37] Harpe, P.; Cui Zhou; Xiaoyan Wang; Dolmans, G.; de Groot, H., "A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.388-389, 7-11 Feb. 2010
[38] Rabuske, T.G.; Rabuske, T.G.; Rodrigues, C.R., "A novel energy efficient digital controller for charge sharing successive approximation ADC," in Circuits and Systems (LASCAS), 2011 IEEE Second Latin American Symposium on , vol., no., pp.1-4, 23-25 Feb. 2011
[39] Kuntz, T.G.R.; Rodrigues, C.R.; Nooshabadi, S., "An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm," in Circuits and Systems (ISCAS), 2011 IEEE International Symposium on , vol., no., pp.261-264, 15-18 May 2011
[40] Galton, I., "Why Dynamic-Element-Matching DACs Work," in Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.57, no.2, pp.69-74, Feb. 2010
[41] Souri, K.; Makinwa, K.A.A., "A 0.12mm2 7.4μW Micropower Temperature Sensor With an Inaccuracy of ±0.2oC (3σ) From 30oC to 125oC," in Solid-State Circuits, IEEE Journal of , vol.46, no.7, pp.1693-1700, July 2011
[42] Souri, K.; Youngcheol Chae; Makinwa, K.A.A., "A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of ±0.15oC (3σ) From 55oC to 125oC," in Solid-State Circuits, IEEE Journal of , vol.48, no.1, pp.292-301, Jan. 2013
[43] Fredenburg, J.A.; Flynn, M.P., "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," in Solid-State Circuits, IEEE Journal of , vol.47, no.12, pp.2898-2904, Dec. 2012
[44] Choksi, O.; Carley, L.R., "Analysis of switched-capacitor common-mode feedback circuit," in Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.50, no.12, pp.906-917, Dec. 2003
[45] D. Garrity and P. Rakers, “Common-mode output sensing circuit,” U.S. patent 5,894,284, Apr. 13, 1999.
[46] Zhenglin Yang; Libin Yao; Yong Lian, "A 0.5-V 35-μW 85-dB DR Double-Sampled ΔΣ Modulator for Audio Applications," in Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.722-735, March 2012
[47] Hogenauer, E., "An economical class of digital filters for decimation and interpolation," in Acoustics, Speech and Signal Processing, IEEE Transactions on , vol.29, no.2, pp.155-162, Apr 1981
[48] Sechang Oh, Wanyeong Jung, Kaiyuan Yang, D. Blaauw and D. Sylvester, "15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR," VLSI Circuits Digest of Technical Papers, 2014 Symposium on, Honolulu, HI, 2014, pp. 1-2.
[49] S. Billa, A. Sukumaran and S. Pavan, "15.4 A 280??W 24kHz-BW 98.5dB-SNDR chopped single-bit CT DSM achieving <10Hz 1/f noise corner without chopping artifacts," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016, pp. 276-277.
[50] K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho, and A. Matsuzawa, “A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 697-706, Apr. 2010.
[51] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi and G. C. Temes, "A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 494-631.