本論文提出一個可應用於物聯網之十位元低電壓及高能源效率連續近似(SAR)類比數位轉換器(ADC)。
為達到良好功率消耗表現，本論文所提出之類比數位轉換器操作於超低電壓的0.35伏特至0.5伏特。此架構重複利用比較器(comparator)，在比較雙端輸入電壓值時，同時將輸入電壓轉化成時域資訊，並利用時域量化器(time-domain quantizer)在同一比較週期內直接判斷輸入電壓之電壓範圍。此類比數位轉換器基於Vcm-based切換方式提出具輸入電壓適應性(input-range-adaptive)的電容切換方式，此方式可以維持固定的共模準位電壓，並大幅節省類比數位轉換器(DAC)之電容切換耗能。
為驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，晶片總面積為1133×1133μm2，核心電路面積為390×97μm2，在0.35至0.5伏特電源電壓及相對應的300千至2百萬赫茲取樣頻率操作下，此晶片在Nyquist頻率訊號輸入時實現之SNDR為從55.5至56.3dB，其對應的ENOB為8.92至9.06bit，功率消耗為0.3至2.5微瓦，等效的figure of merit (FoM)為1.94至2.32fJ/conversion-step。

This thesis presents an ultra-low voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) for Internet of Things (IoT).
The proposed ADC operates at ultra-low supply voltage from 0.35V to 0.5V to save power consumption. This architecture reuses a comparator as a voltage-to-time converter and implements a time-domain quantizer. The comparator converts voltage difference of input signal sampled on DACs to MSB result and the corresponding comparison time simultaneously, and then time-domain quantizer detects the input range. An input-range-adaptive (IRA) switching method is proposed to significantly reduce the average switching power of capacitive-DAC (CDAC) and keep common-mode voltage constant.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 390×97μm2. At 0.35V-to-0.5V supply voltage and 300kS/s-to-2MS/s sampling rate, the ADC achieves SNDR from 55.5dB to 56.3dB corresponding ENOB from 8.92bit to 9.06bit at Nyquist-frequency input and consumes power from 0.3μW to 2.5μW, resulting in a figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32fJ/conversion-step.

Content
Abstract ii
Content iii
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Architecture Selection 2
1.2 Performance Metrics of SAR ADC 4
1.2.1 Nyquist Criterion 4
1.2.2 Resolution 5
1.2.3 Quantization Error 5
1.2.4 Offset and Gain Error 6
1.2.5 Differential Nonlinearity 7
1.2.6 Integral Nonlinearity 7
1.2.7 Signal-to-Noise Ratio 8
1.2.8 Dynamic Range 8
1.2.9 Figure of Merit 9
1.3 Target Specifications 9
1.4 Thesis Organization 10
Chapter 2 Successive Approximation Register ADC Overview 11
2.1 Introduction 11
2.2 Operation Procedure of Conventional SAR ADC 12
2.3 Considerations of Sample and Hold 13
2.3.1 KT/C Noise 14
2.3.2 Sampling Speed 14
2.3.3 Charge Injection 15
2.3.4 Clock Feedthrough 16
2.4 Considerations of Capacitive DAC 17
2.4.1 DAC Parasitic Capacitance 18
2.4.2 DAC Capacitor Mismatch 19
2.4.3 Settling Time 19
2.5 Considerations of Comparator 20
2.5.1 Input Offset 21
2.5.2 Kickback Noise 22
2.6 SAR Control Logic 22
2.7 Summary 24
Chapter 3 Circuit Design Considerations 25
3.1 Differential SAR ADC 25
3.2 CDAC Switching Energy 26
3.2.1 Conventional DAC Switching 27
3.2.2 Monotonic DAC Switching 30
3.2.3 Vcm-Based DAC Switching 32
3.2.4 Proposed Input Range Adaptive Switching Technique 34
3.3 Comparator 36
3.4 Time-Domain Quantizer 37
3.5 Sample and Hold 39
3.6 Digital SAR Control Logic 40
3.7 Summary 41
Chapter 4 Circuit Implementation of Successive Approximation ADC 43
4.1 Architecture of Proposed SAR ADC 43
4.2 Design of Sample and Hold 47
4.3 Design of Capacitive DAC 48
4.4 Design of Comparator 50
4.5 Design of Time-Domain Quantizer 51
4.6 Digital Control Logic 53
4.7 Calibration Procedure 55
4.7.1 Calibration of Comparator 56
4.7.2 Calibration of Delay Element 56
4.8 Pre-Layout and Post-Layout Simulations 57
4.9 Summary 59
Chapter 5 Measurement Results 61
5.1 Measurement Environment Setup 61
5.2 Measurement Results 61
5.2.1 Static Performance 62
5.2.2 Dynamic Performance 63
5.2.3 Performance Discussion 65
5.3 Performance Summary and Comparison 69
5.4 Summary 71
Chapter 6 Conclusion and Future Work 73
6.1 Conclusion 73
6.2 Future Work 73
Bibliography 75

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