傳統記憶體的架構與介面是針對單核心單線程的系統做設計,但是隨著電子設備的演 進,這些記憶體並不適用於多核心的中央運算單元以及手持電子裝置等等系統。除了對讀 寫速度的要求以外,高資料吞吐量與低功耗的性能也越來越受到重視。近年來不論是業界 或學術界,都有許多新的記憶體標準和架構被提出來,希望能解決未來記憶體系統的需求。 為了要能夠評估各種不同記憶體在系統中的表現,勢必要能夠針對這些記憶體系統進行模 擬。
現在大部份的記憶體模擬器,像是 DRAMSim2 或者 USIMM,都只能針對某一種特 定架構的記憶體做模擬。如果使用者想要建立其他記憶體的模擬環境,必須去修改這些模 擬器的程式碼。但是這些模擬器的程式碼都和他們的目標記憶體架構有高度的耦合性,因 此若要改寫程式來符合另一種記憶體的架構或介面,必須付出不少的心力。
為了讓使用者能夠更方便而且快速的模擬不同的記憶體,我們用 SystemC 建立了一 個可調式記憶體系統模擬器:FlexDRAM。FlexDRAM 讓使用者可以編寫一個設定檔來建 構目標記憶體的階層架構(hierarchy),並且設定符合該記憶體操作的時間限制(timing constraints)。當模擬器接受這些設定以後,就能夠以簡單的記憶體控制器來操作記憶體 而不違反目標記憶體的操作時間限制。若使用者想要設計記憶體控制器來最佳化系統,也 可以去改寫 SystemC 的 Scheduler 模組。FlexDRAM 提供了一些 API,方便使用者設 計記憶體控制器。
為了與其他模擬器做比較,我們設計了一個跟 DRAMSim2 一樣的記憶體控制器, 跑相同的記憶體追蹤檔案(memory trace file)並且比較輸出的時間。模擬結果顯示我們 能夠有跟 DRAMSim2 一樣的行為。

In the past, several new DRAM architectures are proposed to meet requirements of bandwidth growth, latency reduction and energy consumption instead of standard DDR interfaces. To evaluate the effectiveness of new memory systems, it is necessary to run simulations.
Most existing DRAM simulators are built for a specific type of DRAM. To evaluate new mem- ory systems, one have to modify codes of those simulators. But it is not always easy because the codebases are blended with structure of original target DRAM.
Due to the lack of flexible simulation tool, we developed a cycle-accurate DRAM system sim- ulator in SystemC - FlexDRAM. It can be configured according to the different specifications of DRAM die. Users can describe the DRAM structure and timing constraints in a configuration file, and write their own memory controller with the provided APIs. It is easy to build a memory sys- tem for new DRAM types. The proposed simulator was implemented and benchmarked against a DRAMSim2 simulator. The simulator can produce the same timing results as DRAMSim2.

1 Introduction 6
1.1 Motivation....................................... 6
1.2 Organization...................................... 7
2 Background 8
2.1 RelatedWorks..................................... 8
2.2 ChallengesofModelingDRAM ........................... 9
2.3 BasicDRAMConcepts................................ 10
2.3.1 DRAMCell.................................. 10
2.3.2 BankandBankOperations.......................... 10
2.3.3 DRAMDevice ................................ 11 2.3.4 MemoryController.............................. 12
2.3.5 DRAMTimings ............................... 12
3 Proposed DRAM Simulator - FlexDRAM 15
3.1 Overview ....................................... 15
3.2 ModulesintheSimulator............................... 16
3.3 DRAMHierarchyRepresentation .......................... 17
3.4 Bank.......................................... 19
3.5 HierarchyLabel.................................... 19
3.5.1 HierarchyDifference............................. 20
3.6 TimingConstraintTable ............................... 22
3.7 ConfigurationFile................................... 24
3.7.1 BuildHierarchy................................ 24
3.7.2 AddressMapping............................... 26
3.7.3 ConfigureTiming............................... 27
3.8 CustomizeMemoryController ............................ 29
4 Experiment 31
4.1 CustomizeMemoryController ............................ 31
4.2 ConfigurationFile................................... 33
4.3 TraceFiles....................................... 35
4.4 ExperimentalResultandAnalysis .......................... 36
4.4.1 SimulationSpeed............................... 36
5 Conclusion and Future Work 38
5.1 Conclusion ...................................... 38
5.2 FutureWork...................................... 38
5.2.1 CompleteDRAMFunctions ......................... 38
5.2.2 ImproveSimulationSpeed.......................... 39
5.2.3 PowerEstimation............................... 39
5.2.4 IntegratewithDArT ............................. 39
5.2.5 FullSystemSimulation............................ 39

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