當在軟體上實現高碼率(coderate)的低密度奇偶檢查碼(Low-DensityParityCheckCodes,LDPCcodes)時，我們需要投入大量的模擬時間才能看到比較高信噪比(Signal-to-noiseratio,SNR)的模擬結果。但如果想要觀察到更高信噪比的結果甚至到發生誤碼平層(errorfloor)的資料點，需要耗費至少數十年的時間才能完成。因此本篇論文提出把相關的編解碼器及訊號產生器，加性高斯白雜訊(AdditivewhiteGaussiannoise,AWGN)頻道以及錯誤比對電路實作到硬體上，透過合成及繞線後放到現場可編輯邏輯閘陣列(Field-ProgrammableGateArray,FPGA)上面運作，如此即可用相對於軟體好幾千倍的速度來完成模擬，達到短時間內看到高信噪比資料的目的。
除此之外,不同循環(circulant)和大小(size)的校驗矩陣在瀑布(waterfall)及誤碼平層上的表現皆有差異，為了檢驗出最符合我們需求的校驗矩陣，我們需要大量測試這些可能達到我們要求的矩陣。但每更換一個矩陣，編碼需要的資訊或解碼需要的排程都要重新修改。本篇論文為了減少在更換檢驗矩陣上花費的時間，提出了彈性修改編解碼器的方法。這個方法可以在短時間內產生出指定矩陣編解碼器的排程及相關電路，如此一來即可更快看到模擬的結果。

It is hard to obtain error-floor results of Low-Density Parity Check Codes(LDPC codes) in a short time using software simulation, especially for LDPC codes with excellent error
oor performance. So we construct a Field-Programmable Gate Array (FPGA) platform to verify the error floor performance. This
platform can process much more faster than software simulation. In addition,we propose a method to make LDPC codec more
exible such that a variety of LDPC codes with different parity check matrices (PCMs) can be veried in a short time. A uncorrectable BER of 10􀀀^-14 can be veried using the proposed
platform.

1.簡介
2.低密度奇偶檢查碼回顧
3.彈性產生低密度奇偶編解碼器
4.現場可編輯邏輯閘平台建立
5.實做與驗證結果
6.結論

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