本研究以TSMC 0.18um 1P6M CMOS標準製程來設計並實現Pirani真空計。一般而言，Pirani真空計由發熱源與散熱片所組成，利用空氣熱傳導係數隨壓力而變的特性，發熱源所產生的熱透過空氣傳遞至散熱片的熱量將會不同，因此可利用此特性來量測壓力變化。本研究提出新型態的結構設計，使元件的熱阻(Thermal resistance)可以上升，透過熱阻的上升使元件在相同功率下可以有較高的升溫，因而增加熱源與散熱片間的熱傳效率，以提升元件的性能。本研究共提出兩種新型結構設計，以達到在相同面積大小的情況下增加元件使用性能的目標。第一種結構設計為互補式內置散熱片結構設計，此設計具有以下特點：(1)熱源上挖洞的設計可以增加元件的熱阻。(2)內置散熱片結構設計彌補因挖洞而損失的有效面積。(3)以金屬作為加熱源使感測材料與散熱源間沒有太多二氧化矽阻隔，大幅提升元件靈敏度。(4)可輕易與其他CMOS-MEMS元件作封裝整合，以檢測封裝內部真空度。第二種結構設計為互補式凸型散熱片與凹槽熱源結構設計，此設計具有以下特點：(1)凸型散熱片垂直整合於凹槽熱源中可增加有效散熱面積。(2)凹槽熱源設計可以增加元件的熱阻。(3)可輕易與其他CMOS-MEMS元件作封裝整合，以檢測封裝內部真空度。

This study employs standard TSMC 0.18um 1P6M CMOS process to design and implement Pirani vacuum gauge. Generally, Pirani vacuum gauge consists of heater and heat sink units. The heat generated by heater is transferred to the heat sink through gas molecules whose thermal conductivity depends on their pressure. This study proposes a novel structure design to improve the performance of Pirani vacuum gauge which is increasing the thermal resistance of heater. By increasing thermal resistance, the heater can obtain higher temperature comparing to typical one under the same power heating. Therefore, the efficiency of heat transfer can be increased and further improve the performance of the gauge. This study presents two different structures to achieve the goal of improving the device performance without changing device footprint size. Firstly, this study presents a complementary inbuilt heat sink design. This design has the following advantages: (1) The hole in heater can increase thermal resistance of heater, (2) The inbuilt heat sinks compensate the lost active area, (3) The heating and sensing material is composed of metal, so there are no much SiO2 to influence the heat transfer, and (4) Easy integration with packaged CMOS-MEMS devices for pressure monitoring. Then, this study presents another complementary bump heat sink and cavity heater design. This design has the following advantages: (1) The bump heat sink vertical integrates with cavity heater increases the active area, (2) The cavity in heater increases thermal resistance of heater, and (3) Easy integration with packaged CMOS-MEMS devices for pressure monitoring.

中文摘要 i
Abstract ii
致謝 iii
目錄 v
圖目錄 viii
表目錄 xiv
第一章 緒論 1
1-1 前言 1
1-2 研究動機 3
1-3 文獻回顧 4
1-3-1 封裝檢測方式 4
1-3-2 Pirani真空計 6
1-3-3 CMOS-MEMS製程 10
1-4 研究目標與架構 12
第二章 理論分析 26
2-1 不同壓力下之熱傳探討 26
2-2 Pirani真空計理論分析 28
2-1-1 操作原理及其物理意義 28
2-2-2 理論公式 30
2-2-3 多層膜公式修正 32
2-3 模擬與分析 32
第三章 互補式內置散熱片結構設計 40
3-1 結構設計與分析 40
3-2 元件製程與結果 43
3-2-1 TSMC 0.18μm 1P6M CMOS製程 43
3-2-2 CMOS-MEMS元件定義與後製程 44
3-2-3 製程結果與討論 46
3-3 量測結果與討論 47
3-3-1 材料特性量測 47
3-3-2 元件特性量測 48
3-4 小結 54
第四章 互補式凸型散熱片與凹槽熱源結構設計 70
4-1 結構設計與分析 70
4-2 元件後製程與結果 73
4-3 量測結果與討論 74
4-3-1 材料特性量測 75
4-3-2 元件特性量測 76
4-4 小結 79
第五章 結論與未來工作 95
5-1 研究成果 95
5-2 未來工作 97
參考文獻 106

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