隨著筆記型電腦，智慧型手機等手持式電子產品市場的發展，CMOS元件的技術節點必須不斷微縮，以期能達到試場需求。且CMOS元件在進行尺寸微縮的研發時，仍必須維持(1)高效能、(2)低功耗、(3)低的IC成本。但是傳統的金氧半場效應電晶體(MOSFET)會隨著尺度的微縮，遭遇到相當多的問題。例如：摻雜物的不規則分布、熱預算的問題以及短通道效應等。而穿隧式場效應電晶體和無接面式場效應電晶體正是被用來解決上述問題的新穎元件。
本論文共分為四個部份，(1) 非對稱閘極之穿隧式場效應電晶體，(2)將微波活化技術應用在穿隧式場效應電晶體，(3)將穿隧式場效應電晶體應用在非揮發性記憶體，(4)矽與鍺的超薄通道(1奈米)與超短通道(1奈米與3奈米)之無接面式場效應電晶體，以及環繞式閘極與單層矽原子通道之無接面式場效應電晶體，其次臨界擺幅可達43 mV/decade。
在第一部份介紹非對稱閘極之穿隧式場效應電晶體，其結構結合了環繞式閘極與平面式閘極，利用源極需要較小的Screening length及汲極需要較大的Screening length之特性，大幅提高穿隧式場效應電晶體的效能。從模擬結果來看，次臨界擺幅以及開關電流比值皆有顯著提升。更重要的是，此非對稱結構相當容易與傳統CMOS元件製程結合，僅需要改變閘極曝光的光罩即可達成，無須額外的複雜製程。
第二部份比較了低溫的微波活化和高溫的快速升溫熱退火應用再穿隧式場效應電晶體。由實驗結果可以得知，低溫的微波活化能得到較小的Screening length。因此，穿隧式場效應電晶體利用微波來活化摻雜物，可以得到較小的次臨界擺幅，較大的開關電流比值，幾乎可以忽略的短通道效應。
第三部份，我們首次做出了具有大記憶窗的鰭式與穿隧式SONOS非揮發性記憶體(T-SONOS)。此鰭式與穿隧式SONOS非揮發性記憶體可以利用所有的寫入機制來進行寫入，包含了FN穿隧，熱載子注入，帶至帶的熱載子注入。此外，鰭式結構也提供了優秀的次臨界擺幅以及開關電流比值。此結構在寫入後，記憶窗可達4.7V，其歸功於鰭式結構提供了較集中的電場，而我們也利用TCAD模擬來驗證。因此，鰭式結構比平面式結構有更高的寫入抹除速度。在FN穿隧操作下，鰭式結構的T-SONOS在經過十年後仍可保存65%的記憶窗，與傳統非揮發性記憶體相近。在熱載子注入，帶至帶的熱載子注入操作下，經過一萬次的寫抹後，仍可保存74%的記憶窗。而熱載子注入操作下，在經過十年後仍可保存81%的記憶窗，帶至帶的熱載子注入則可以保存65%的記憶窗。
在第四部份，矽與鍺的超薄通道(1奈米)與超短通道(1奈米與3奈米)之無接面式場效應電晶體被成功的探討。此超薄通道可藉由量子效應來達到相當低的漏電流。且藉由量子效應的幫助，矽與鍺的無接面式場效應電晶體可微縮至1奈米與3奈米仍保有105的開關電流比值，且SNM亦達到業界要求。此外，只要利用簡單的乾式蝕刻技術，即可完成此結構。
此外，我們成功製做出擁有通道僅有0.65奈米厚的多晶矽環繞式閘極之無接面式場效應電晶體。此電晶體的最小次臨界擺幅為43 mV/decade，平均次臨界擺幅為59 mV/decade，比物理極限(60 mV/decade)還要低。由模擬結果顯示，此優異電性可歸功於0.65奈米厚的通道，因為此超薄通道可以產生帶至帶的穿隧效應，藉由此量子效應，可使次臨界擺幅打破物理極限。

With the rapid development of the market for portable products, including notebooks and smart-phones, a complementary metal oxide semiconductor (CMOS) technology must be scaled to meet market demand. The scaled transistors should meet (1) high performance, (2) low power and (3) low cost per transistor for integrated circuit (IC). But the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer a lot of challenges when feature size is being scaled down, such as random dopant fluctuation, thermal budgets and short channel effect (SCE). Therefore, tunnel field-effect transistor and junctionless field-effect transistor have been researching for scaling device.
This thesis is divided into five parts to demonstrate (1) asymmetrical-gate tunnel field-effect transistor, (2) microwave annealing for tunnel field-effect transistor, (3) tunnel field-effect transistor SONOS nonvolatile memory, (4) silicon and germanium ultra-thin body (1 nm) junctionless field-effect transistor with ultra-short gate length (1 nm and 3 nm), (5) gate-all-around junctionless with Si monolayer channel (0.65 nm) and steep subthreshold swing (43 mV/decade).
In the first part, an asymmetrical-gate TFET, which combines the advantages of the GAA TFET and the planar TFET, and has to provide different screening lengths on the source side and drain side. Therefore, both the minimum SS and the ION/IOFF ratio are improved. An asymmetric-gate structure is easily fabricated as an actual device by simply changing the layout of gate in a general CMOS fabrication. Accordingly, the GAA part and the planar part of the gate are fabricated simultaneously without the need for a complicated process.
In the second part, different means of activating dopants in FinTFETs including MWA and high-temperature RTA were compared. Microwave annealing yielded a lower λ than RTA. Therefore, the FinTFET that was annealed by MWA had a higher ON/OFF current ratio, a smaller VBTBT, and a lower SS than that was annealed by RTA. Additionally, FinTFET that was annealed by MWA had an almost negligible DIBL. Accordingly, microwave annealing has potential application in future TFET technology.
In the third part, a fin-shaped T-SONOS NVM with a large memory window and high reliability had been demonstrated. All program mechanisms including FN, CHE and BBHE can be used in single device. As well as improving the performance of T-SONOS NVM in terms of SS and ION/IOFF, a fin-shaped structure moves equipotential line closer to the source side. Such structure also produces a large memory window (4.7 V at VG = 17 V, tP = 1 ms) because the corners of the NWs have stronger electrical fields than the other parts, as has been demonstrated by TCAD simulation. Accordingly, fin-shaped T-SONOS NVM has a higher programming and erasing speed than does planar T-SONOS NVM. Under the FN programming mechanism, the fin-shaped T-SONOS NVM reveals that 65% of the original memory window is retained after ten years because the discrete charge trapping properties of nitride make this memory as reliable as conventional NVM. Moreover, this device also exhibits better endurance, 74%, after 104 P/E cycles of CHE programming and BBHE programming. After ten years of CHE programming, 81% of the original memory window is retained and after the same period of BBHE programming, 65% is retained. Therefore, fin-shaped T-SONOS NVM is suitable for use in portable devices with low standby power consumption.
In the fourth part, Si and Ge UTB-JLFET with LG = 1 nm and LG = 3 nm were demonstrated successfully. The off-state leakage current can be reduced by quantum confinement effect. As UTB is employed, Si and Ge UTB-JLFET with LG = 1 nm have high ION/IOFF current ratio of 105 at VG = 1 V. Moreover, Ge UTB-JLFET with LG = 1 nm and LG = 3 nm have reasonable SNM that can meet the industry requirements. Using FIB or RIE, this UTB structure can be achieved in sub-5 nm CMOS technology nodes. And this device can integrate high-k/metal-gate by ALD and CMP. Finally, circuit performances reveal UTB-JLFET can be used in advanced logic ICs applications.
Finally, a poly-Si GAA trench JLFET with ultra-thin channel (0.65 nm-thick) had been successfully demonstrated. This device has steeper SSmin of 43 mV/decade and SSavg of 59 mV/decade because of full depletion in ultra-thin channel. The simulation results indicated there are BTBT generation at the channel/drain junction region. Finally, the ION/IOFF of this device is higher than 108.

Contents
Contents ix
Table Captions xii
Figure Captions xiii
Chapter 1 1
Introduction 1
1-1 Conventional MOSFETs 1
1-2 Challenges of Conventional MOSFETs 3
1-3 Multi-gate structure 4
1-4 Tunnel Field-Effect Transistors 5
A. Basic Mechanisms 6
B. Screening Length 7
1-5 Junctionless Field-Effect Transistors 8
A. Basic Mechanisms 8
B. Short channel behavior of Junctionless Field-Effect Transistors 10
1-6 Motivation 11
A. Asymmetrical-Gate Tunnel Field-Effect Transistor 11
B. Microwave Annealing for Tunnel Field-Effect Transistor 11
C. Pi-gate tunneling field-effect transistor charge trapping nonvolatile memory based on all tunneling transportation 11
D. Performance Evaluation of Silicon and Germanium Ultrathin Body (1 nm) Junctionless Field-Effect Transistor With Ultra short Gate Length 12
E. Gate-All-Around Junctionless Field-Effect Transistor with Si Monolayer channel (0.65 nm) and Steep Subthreshold Swing (43 mV/decade) 13
1-7 Organization 13
Chapter 2 30
Nonvolatile Memory 30
2-1 Basic Mechanism of Nonvolatile Memory 30
2-2 Program Mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection and band-to-band tunneling-induced hot electron (BBHE) 30
A. Fowler-Nordheim (FN) tunneling 30
B. Channel hot-electron (CHE) injection 31
C. Band-to-Band tunneling-induced hot electron (BBHE) 32
2-3 Erase Mechanism (Fowler-Nordheim (FN) tunneling) 34
2-4 Program/Erase Speed 34
2-5 Reliability (Endurance, Retention) 34
A. Endurance 35
B. Retention 36
Chapter 3 44
Asymmetrical-Gate Tunnel Field-Effect Transistor 44
3-1 Device Structure and Simulation Models 44
3-2 Simulation Results and Discussion 47
3-3 Band-to-Band Generation Rate 48
3-4 Output Characteristics 49
3-5 Summary of This Chapter 49
Chapter 4 54
Microwave Annealing for Tunnel Field-Effect Transistor 54
4-1 Device Fabrication 54
4-2 Results and Discussion 55
4-3 Conclusion 58
Chapter 5 62
Pi-gate tunneling field-effect transistor charge trapping nonvolatile memory based on all tunneling transportation 62
5-1 Device Structure and Simulation Models 62
5-2 Results and Discussion 65
A. Program by FN Tunneling 66
B. Programming by Channel Hot-Electron Injection 67
C. Programming by Band-to-Band Tunneling-Induced Hot Electrons 68
D. Comparison of T-SONOS with conventional NVM 69
5-3 Conclusion 70
Chapter 6 79
Junctionless Field-Effect Transistor With Ultra short Gate Length And Ultrathin Body 79
6-1 Silicon and Germanium Junctionless Field-Effect Transistor With Ultra short Gate Length 79
A. Device Structure and Simulation models 79
B. Results and Discussion 80
6-2 Gate-All-Around Junctionless Field-Effect Transistor with Si Monolayer channel (0.65 nm) and Steep Subthreshold Swing (43 mV/decade) 82
A. Device Fabrication 82
B. Results and Discussion 82
6-3 Conclusion 85
Chapter 7 101
Conclusion 101
Chapter 8 104
Future Works 104
Reference 107
簡歷 126
著作目錄(Publication list) 127

Chapter 1
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[1-48] S. Jin, A.-T. Pham, W. Choi, Y. Nishizawa, Y.-T. Kim, K.-H. Lee, Y. Park, and E. S. Jung, “Performance Evaluation of InGaAs, Si, and Ge nFinFETs based on Coupled 3D Drift-Diffusion/Multisubband Boltzmann Transport Equations Solver,” in IEDM Tech. Dig., Dec. 2014, pp. 7.5.1-7.5.4.
[1-49] S. Migita, Y. Morita, T. Matsukawa, M. Masahara and H. Ota,, “Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI,” IEEE Trans. Nanotechnol. vol. 13, no. 2, pp. 208–215, Jan. 2014.
Chapter 2
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Chapter 3
[3-1] K. Jeon, W. Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H. H. Tseng, R. Jammy, T. J. King Liu, and C. Hu, “Si tunnel transistors with a novel silicided source and 46mV/dec swing,” in VLSI Symp. Tech. Dig., June 2010, pp. 121-122.
[3-2] S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K. Bourdelle, Q. T. Zhao, and S. Mantl, “Ω-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs,” IEEE Electron Device Lett., vol. 33, pp. 1535-1537, Nov. 2012.
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[3-9] Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, and Y. Wang, “A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration,” in IEDM Tech. Dig., Dec. 2012, pp. 8.5.1-8.5.4.
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Chapter 4
[4-1] R. Asra, M. Shrivastava, K. V. R. M. Murali, R. K. Pandey, H. Gossner, and V. R. Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1855–1863, Nov. 2011.
[4-2] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011.
[4-3] K. Jeon, W. Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H. H. Tseng, R. Jammy, T. J. King Liu, and C. Hu, “Si tunnel transistors with a novel silicided source and 46mV/dec swing,” in VLSI Symp. Tech. Dig., Jun. 2010, pp. 121-122.
[4-4] J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics, vol. 48, pp. 897–905, Jun. 2004.
[4-5] J. T. Smith, C. Sandow, S. Das, R. A. Minamisawa, S. Mantl, and Joerg Appenzeller, “Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1822–1829, Jul. 2011.
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[4-9] C. H. Kim, K.-S. Sohn, and J. Jang, “Temperature dependent leakage currents in polycrystalline silicon thin film transistors,” J. Appl. Phys, vol. 81, pp. 8084, Jun. 1997.
[4-10] S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K. Bourdelle, Q. T. Zhao, and S. Mantl, “Ω-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs,” IEEE Electron Device Lett., vol. 33, pp. 1535-1537, Nov. 2012.
Chapter 5
[5-1] Synopsys TCAD, Version E-2010.12.
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[5-3] Y. C. Wu, M. F. Hung, C. W. Chang, and P. W. Su, “Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics,” Appl Phys Lett., vol. 92, pp. 163506, Apr. 2008.
[5-4] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, C. C. Ko, S. Yang., L. W. Feng, S. M. Sze, C. Y. Chang, and C. H. Lien, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications,” Appl Phys Lett., vol. 91, pp. 213101, Nov. 2007.
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[5-7] Y. C. Wu, C. Y. Chang, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Ta, and S. M. Sze, “High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels,” in IEDM Symp. Tech. Dig., Dec. 2004, pp.777-780.
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[5-11] H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.-Y. Wang, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, and C.-Y. Lu, “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” in VLSI Symp. Tech. Dig., June 2010, pp. 131-132.
[5-12] J.-. Hwang, T.-L. Lee, H.-C. Ma, T.-C. Lee, T.-H. Chung, C.-Y. Chang, S.-D. Liu, B.-C. Perng, J.-W. Hsu, M.-Y. Lee, C.-Y. Ting, C.-C. Huang, J.-H. Wang, J.-H. Shieh, and F.-L. Yang, “20nm Gate Bulk-FinFET SONOS Flash,” in IEDM Symp. Tech. Dig., Dec. 2005, pp.154-157.
[5-13] H.-T. Lue, S.-Y. Wang, E.-K. Lai, M.-T. Wu, L.-W. Yang, K.-C. Chen, J. Ku, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A Novel P-Channel NAND-Type Flash Memory with 2-bit/cell Operation and High Programming Throughput (>20 MB/sec),” in IEDM Symp. Tech. Dig., Dec. 2005, pp.331-334.
Chapter 6
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[6-3] Y. Kamata, Y. Kamimuta, K. Ikeda, K. Furuse, M. Ono, M. Oda, Y. Moriyama, K. Usuda, M. Koike, T. Irisawa, E. Kurosawa, and T. Tezuka, “Superior Cut-Off Characteristics of Lg=40nm Wfin=7nm Poly Ge Junctionless Tri-gate FET for Stacked 3D Circuits Integration,” in VLSI Symp. Tech. Dig., June 2013, pp. 94-95.
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[6-6] W. Guo, M. Choi, A. Rouhi, V. Moroz, G. Eneman, J. Mitard, L. Witters, G. Van der Plas, N. Collaert, G. Beyer, P. Absil, A. Thean, and E. Beyne, “Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime,” in IEDM Tech. Dig., Dec. 2014, pp. 7.1.1-7.1.4.
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[6-9] S. Migita, Y. Morita, T. Matsukawa, M. Masahara and H. Ota,, “Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI,” IEEE Trans. Nanotechnol. vol. 13, pp.208, 2014.
[6-10] Kian Hui Goh, Yan Guo, Xiao Gong, Geng-Chiau Liang and Yee-Chia Yeo, “Near Ballistic Sub-7 nm Junctionless FET Featuring 1 nm Extremely-Thin Channel and Raised S/D Structure,” in IEDM Tech. Dig., Dec. 2013, pp. 433-436.
[6-11] Mu-Shih Yeh, Yung-Chun Wu, Min-Hsin Wu, Yi-Ruei Jhan, Ming-Hsien Chung, and Min-Feng Hung, “High Performance Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure,” in IEDM Tech. Dig., Dec. 2014, pp. 618-621.
[6-12] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011.
[6-13] Synopsys TCAD, Version J-2014.09.