近年來，快閃記憶體的需求量大幅上升。然而，在元件日漸微縮的趨勢下，平面式元件微縮空間有限，造成元件密度難增且製程難度跟著大幅的提升，因此如何提高電性又要能降低製程難度為目前最重要的課題之一。有些解決方法已漸漸被提出，如複晶矽的使用、矽化鍺材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用等等。本篇論文以矽化鍺掩埋式通道為主軸，將其應用在奈米線通道複晶矽快閃記憶體元件上，加以研究並探討電性的表現。
第一個實驗首次將矽化鍺掩埋式通道應用在複晶矽反轉式快閃記憶體元件上。本實驗中，將矽化鍺和矽覆蓋層成長於反轉式記憶體的奈米線通道上，將其與無成長的反轉式奈米線通道式快閃記憶體元件做比較。有成長的元件在寫入速度和抹除速度上都有較好的表現，電荷保持力特性的表現上也和沒有成長的元件相差不多，而電荷耐久力有成長的元件則是因為有著較快的寫抹速度降低氧化層的損傷而在耐久力有較優秀的表現。
第二個實驗中則是將矽化鍺掩埋式通道製作在複晶矽無接面奈米線通道式的快閃記憶體元件上，並與電荷反轉式奈米線通道式快閃記憶體元件做比較。無接面元件成長後仍維持了較佳的寫入速度和可靠度特性，且在抹除速度方面也能有所提升，和電荷反轉式元件已可相互比擬。
第三個實驗承襲第二個實驗一樣採用複晶矽無接面式奈米線通道式的快閃記憶體元件，主要探討在不同通道濃度下的無接面式記憶體元件，在成長矽鍺層後的各種電性表現，我們發現成長後通道濃度較濃的無接面式記憶體元件，寫入速度跟抹除速度都會比通道濃度較低的無接面式記憶體元件來的快，各種可靠度特性也都比濃度較低的無接面式記憶體來的優秀，可見通道濃度在經過成長後的無接面式奈米線通道記憶體元件依舊式非常重要的調變參數。

Recently, the flash memory devices with some advantages like low power waste, higher device density, and portable device are more needed. However, as the devices become smaller, there is limited space for planar devices to microminiaturize which makes the the process flow becomes more difficult. How to improve the device characteristic and make the process easier at the same time becomes one of the most important issuestoday. Some solutions have been reported like the implement of SiGe, nanowire channel structure, and junctionless mode flash memory devices etc. In this thesis, we implemented the SiGe buried channel on the Poly-Si nanowire channel flash memory devices, and find out the devices electronic characteristic.
In the first experiment, we try to apply the SiGe buried channel on the inversion-mode flash memory device. We grew SiGe and Si capping layer onthe nanowire channel of the inversion-mode flash memory devices. We compared the epitaxial device with the non-grownl one. We found that the device with SiGe showed higher P/E speed, better endurance and similar retention compared to the non-epitaxial one.
In the second experiment, we implemented the SiGe buried channel structure on the junctionless nanowire flash memory devices. We want to know if the SiGe buried channel can also improve the performance on the junctionless devices. The result show that the junctionless devices still performed well on the programming speed and reliability characteristic. Besides, erasing speed became higher after the epitaxy too.
In the third experiment, we want to confirm that if different channel concentration will have any influence on junctionless SiGe buried channel flash memory devices. We found that the heavily doped junctionless devices show better P/E performance and reliability performance which means that the channel concentration is still a important parameter in the SiGe buried channel flash memory devices.

摘要 i
Abstract iii
致謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第一章序論 1
1.1 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕陷式快閃記憶體元件 2
1.2 多晶矽薄膜電晶體 4
1.3多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.4高介電係數材料之介紹 6
1.5 無接面快閃記憶體元件介紹 7
1.6 矽化鍺掩埋式通道的應用 8
1.7各章摘要 9
第二章快閃記憶體元件製程與操作方法 17
2.1 奈米線通道式快閃記憶體元件製程 17
2.1.1 傳統反轉層元件 17
2.1.2 無接面元件 18
2.2 快閃記憶體元件寫入與抹除方法 19
2.2.1 CHEI通道熱電子注入寫入 19
2.2.2 F-N穿隧寫入 20
2.2.3 F-N穿隧抹除 21
2.3 快閃記憶體元件可靠度特性 21
2.3.1 電荷保持力 21
2.3.2 耐久力 22
第三章矽化鍺成長應用在奈米線通道之快閃記憶體元件特性研究 35
3.1 研究動機與背景 36
3.2 實驗 36
3.3 結果與討論 38
3.3.1 元件汲極電流對閘極電壓作圖 38
3.3.2 元件寫入與抹除特性 38
3.3.3 元件可靠度特性 40
3.4 結論 41
第四章矽化鍺成長應用在奈米線通道之無接面快閃記憶體元件特性研究 51
4.1 研究動機與背景 52
4.2 實驗 52
4.3 結果與討論 54
4.3.1 元件汲極電流對閘極電壓作圖 54
4.3.2 元件寫入與抹除特性 55
4.3.3 元件可靠度特性 56
4.4 結論 58
第五章濃度效應對矽化鍺成長應用在奈米線通道之無接面快閃記憶體元件特性研究 68
5.1 研究動機與背景 69
5.2 實驗 69
5.3 結果與討論 71
5.3.1 元件汲極電流對閘極電壓作圖 71
5.3.2 元件寫入與抹除特性 71
5.3.3 元件可靠度特性 73
5.4 結論 74
第六章結論 85
參考文獻 87

[1] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability,”IEEE Electron Device Lett., vol. 42, no. 1, pp. 150 –159, Jan 1995.

[2] M. White, D. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits and Devices Magazine,, vol. 16, no. 4, Jul 2000, pp. 22 –31.

[3] M. White, Y. Yang, A. Purwar, and M. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” in Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, Jun 1996, pp. 52 –57.

[4] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings,2002. IEEE, vol. 5, 2002, pp. 5–2383 – 5–2390 vol.5.

[5] K. Kahng and S. Sze, “A floating gate and its application to memory devices,”IEEE Trans. Electron Devices, vol. 14, no. 9, p. 629, Sep 1967.

[6] A. Wang and W. D. Woo, “Static magnetic storage and delay line,” Journal of Applied Physics, vol. 21, no. 1, pp. 49 –54, Jan 1950.

[7] S. M. Sze and K. K. Ng, physics of semiconductor Devices, 3rdEd., Wiley Interscience, Hoboken, N.J. 2007.

[8] T. Y. Tseng and S. M. Sze, Eds, nonvolatile Memories Materials, Devices, and Applications, American Scientific Publishers, Stevenson Ranch, CA, 2012.

[9] M. H. White,D. A. Adams, and J. Bu, “On the go with SONOS” IEEE Circuits Devices Mag., Vol. 16, No. 4, pp. 22-31, 2000.

[10] N. Yamauchi, J. J. Hajjar and R. Reif, "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film,"IEEE Trans. Electron Devices,vol. 38, pp. 55-60, 1991.


[11] T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, Y. L. Wu, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig. 2007, pp. 913-916.

[12] M. Heyns, S. Beckx, H. Bender, P. Blomme, W. Boullart, B. Brijs, et al., "Scaling of high-k dielectrics towards sub-1nm EOT," in VLSI Technology, Systems, and Applications, 2003 International Symposium on, 2003, pp. 247-250.

[13] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-k metal-gate stack and its MOSFET characteristics,"IEEE Electron Device Lett., vol. 25, pp. 408-410, 2004.

[14] S. C. Lai, H. T. Lue, M. J. Yang, J. Y. Hsieh, S. Y. Wang, T. Wu, G. L. Luo, C. H. Chien, E. K. Lai, K. Y. Hsieh, R. Liu and C. Lu, "MA BE-SONOS: A bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation," in Non-Volatile Semiconductor Memory Workshop, pp. 88-89,2007.

[15] T. Yan-Ny, W. K. Chim, B. Jin Cho, and C. Wee-Kiong, "Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer,"IEEE Electron Device Lett., vol. 51, pp. 1143-1147, 2004.

[16] J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. D. Akhavan, P. Razavi, R. Yan and R. Yu, "Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions,"Sci.Adv.Mater.,vol. 3, pp. 477-482, 2011.

[17] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy and R. Murphy, "Nanowire transistors without junctions,"Nat.Nanotechnol.,vol. 5, pp. 225-229, 2010.

[18] C. J. Su, T. K. Su, T. I. Tsai, H. C. Lin and T. Y. Huang, "A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires,"Nanoscale Res.Lett.,vol. 7, pp. 1-6, 2012.

[19] H. T. Lue, Y. H. Hsiao, P. Y. Du, S. C. Lai, T. H. Hsu, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, C. P. Lu, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, "A novel buried-channel FinFET BE-SONOS NAND flash with improved memory window and cycling endurance," in VLSI Symp. Tech. Dig. 2009, pp. 224-225.

[20] Rui Zhang, Takashi Iwasaki, Noriyuki Taoka, Mitsuru Takenaka, and Shinichi Takagi, “High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation”, IEEE Electron Device Lett., vol. 59, no. 2, pp. 335 –341, Feb 2012.

[21] L. M. Weltzer, and S. K. Banerjee, “Enhanced CHISEL Programming in Flash Memory Devices With SiGe Buried Layer,” Proc. Non-Volatile Memory Technol. Symp.,pp. 31-33, 2004.

[22] D.L.Kencke, Xin Wang, Q. Ouyang, S. Mudanai, A. Tasch , Jr., and S. K. Banjree, “Enhanced secondary electron injection in novel SiGe flash memory devices,” in IEDM Tech. Dig., pp. 105-108, 2000.

[23] Scott C. Wolfson, and Fat Duen Jo, “Transient simulation to analyze flash memory erase improvement due to germanium content in the substrate,” IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2499-2503, Oct. 2010.

[24] Chi-Chao Wang, Kuei-Shu Chang-Liao, Chun-Yuan Lu, and Tien-Ko Wang, “Enhanced Band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification,” IEEE Electron Device Lett., vol. 27, no. 9 pp. 749-751, Sept. 2006.

[25] Li-Jung Liu, Kuei-Shu Chang-Liao, Wen-Chun Keng, and Tien-Ko Wang “Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel,” Solid State Electron., vol. 54, pp. 1113-1118, 2010.

[26] Li-Jung Liu, Kuei-Shu Chang-Liao, Yi-Chuen Jian, Jen-Wei Cheng, and Tien-Ko Wang “Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel,”IEEE Electron Device Lett., vol. 33, no. 9 pp. 1264-1266, Sept. 2012

[27] .Scott C. Wolfson, and Fat Duen Ho, “Transient simulation to analyze flash memory programming improvement due to germanium content in the substrate using nonquasi-static techniques,”Microelectron. Eng., vol. 99, pp. 23-27, Jun. 2012.

[28] B. Van Zeghbroeck, Principles of Semiconductor Devices. Boulder, CO: Univ. Colorado, 2007.

[29] Kuo-Nan Yang, Huan-Tsung Huang, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yo, Simon M. Jang, Douglas C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in P+ poly-gate PMOSFETs with ultrathin gate oxides,”IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2161-2166, Nov 2000.

[30] S. Tam, P.-K. Ko, and C. Hu, “Lucky-electron model of channel hot- electron injection in MOSFET’s,”IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 1116 – 1125, Sep 1984.


[31] M. H. White, Y. Yang, P. Ansha, and M. L. French, "A low voltage SONOS nonvolatile semiconductor memory technology," Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on, vol. 20, pp. 190-195, 1997.

[32] W. Tsai, N. Zous, C. Liu, C. Liu, C. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in Electron Devices Meeting, 2001. IEDM ’01. TechnicalDigest. International, 2001, pp. 32.6.1 –32.6.4.

[33]Y. Sun et al., “Demonstration of memory string with stacked junctionless SONOS realized on vertical silicon nanowire,” in Tech. Dig. IEDM, Dec. 2011, pp. 9.7.1–9.7.4.

[34] S.-J. Choi et al., “A novel junctionless all-around-gate SONOS device
with a quantum nanowire on a bulk substrate for 3D stack NAND flash
memory,” in Symp. VLSI Tech. Dig., Jun. 2011, pp. 74–75.

[35] K.-H. Lee, H. C. Lin, and T. Y. Huang, “A novel charge-trappingtype
memory with gate-all-around poly-Si nanowire and HfAlO trapping
layer,” IEEE Electron Device Lett., vol. 34, no. 3, pp. 393–395,
Mar. 2013.

[36] C. J. Su, T. K. Su, T. I. Tsai, H. C. Lin and T. Y. Huang, "A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires,"Nanoscale Res.Lett., vol. 7, pp. 1-6, 2012.