可攜式產品的普及，對於產品待機時的功率消耗非常注重。但隨著元件臨界電壓的微縮，傳統電晶體面臨次臨界擺幅的極限(60mv/dec@300K)，導致元件的待機電流上升。因此，此篇論文使用的穿隧電晶體是以不同電流機制來突破次臨界擺幅的極限，可以達成微縮元件同時又不失去良好電性的目的。
本文使用P-I-N結構之穿隧電晶體。其利用量子穿隧機制來進行操作，使元件可以經由不同於MOS電晶體飄移電流的穿隧電流來達到快速開關的特性，使元件在OFF的狀態下漏電電流可以減少，達成低功率消耗。
在此篇論文中，我們是第一個提出非對稱閘極穿隧式電晶體的研究。在此研究中我們使用SOI晶圓來製作元件。我們將閘極結構設計於奈米線及平面結構上，形成不對稱的閘極結構。非對稱的閘極結構使閘極對通道控制能力不同，在源極及通道接面上為三項閘極結構，控制能力較佳，使電子的穿隧路徑變小，ION上升。在汲極及通道接面上為平面閘極結構，控制能力較差，使電子穿隧路徑變大，元件的IOFF下降。
非對稱閘極穿隧式電晶體的最小次臨界擺幅達到152mV/dec，平均次臨界擺幅為233mV/dec。其ION可達7×10-7A，IOFF可達1×10-15A，ION/IOFF可達7×108之多。與三向閘極穿隧電晶體結構及平面式穿隧電晶體結構相比有較良好的電性。
我們同時也對非對稱閘極穿隧電晶體做了可靠度的研究，發現元件對positive bias stress以及 hot carrier stress的耐受性較三向閘極穿隧電晶體佳。其原因為非對稱閘極在汲極的平面結構使其電場較小，對元件有較少的破壞。
在本文列出此結構的各項指標，以及實驗數據皆顯示出具鰭式穿隧電晶體具有應用於實際產品的高度價值，同時擁有成為下一世代元件的潛力。

The market demand for portable electric equipment increase dramatically year by year. Although transistors develop toward low cost and high density, maintaining device characteristics becomes difficult due to the device fabrication and physics limitations of the device. Designing a device that different from conventional MOSFET is a necessary way.
This thesis based on P-I-N structure tunnel field effect transistor which operated by quantum tunneling mechanism. Thus, compared with conventional MOSFET operated by drift mechanism, the Tunneling Transistor can achieve fast on/off characteristic and the OFF current can be decrease.
This work is the first time to demonstrate the asymmetric gate tunnel FET. The device is based on SOI wafer. We design the gate structure above nanowire and planar to form asymmetric gate structure. The asymmetric gate structure has different control ability to channel. There is tri-gate structure on source and channel intrinsic junction and the control ability is good. It makes the screening length shorter and leads ION increase. There is planar structure on drain and channel intrinsic junction and the control ability is bad. It makes the screening length longer and leads IOFF smaller than tri-gate tunnel FET.
The asymmetric gate tunnel FET has the SSmin 152mV/dec and SSavg 233mV/dec. ION gets to 7×10-7A and IOFF gets to 1×10-15A. The ON/OFF ration is 7×108. Compare to tri-gate tunnel FET and planar tunnel FET, the AG-TFET has the better electric characteristic.
We also study in the reliability of AG-TFET. In positive bias stress and hot carrier stress analysis, the degradation behaviors after stress are investigated. The AG-TFET presents better reliability than tri-gate TFET after stress. The lesser degradation is due to the peaks of vertical electric field of AG-TFET is lower than tri-gate structure device.
This work shows experimental data for device’s reliability; all the data can display asymmetric gate tunnel field effect transistor has applied to high value actually; it would become the next-generation device.

中文摘要 i

Abstract iii

Acknowledge v

Contents vi

Table Captions viii

Figure Captions ix

Chapter 1 1
Introduction 1
1-1 Introduction of Conventional MOSFET & Low Power Device 1
1-2 Introduction of Tunnel FET Device 9
1-3 Thesis Organization 10

Chapter 2 12
Tunnel FET Mechanism 12
2-1 Basic Principle of Tunnel FET 12
2-2 Screening Length in Tunnel FET 15
2-3 Motivation 19

Chapter 3 21
Device Fabrication and Device Simulation 21
3-1 Device Simulation 21
3-2 Device Fabrication Process 24

Chapter 4 26
Characteristics Analysis 26
4-1 SEM & TEM Analysis 26
4-2 Device Characteristics Analysis 29
4-3 Conclution 35

Chapter 5 36
Reliability Study 36
5-1 High Temperature Performance 36
5-2 Positive Bias Stress Discussion 38
5-3 Hot Carrier Stress Discussion 41
5-4 Conclusion 44

Chapter 6 45

Conclusion 45

Reference 47
Chapter 1 47
Chapter 2 50
Chapter 5 51

Chapter 1
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Chapter 2
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Chapter 5
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