本實驗利用具環繞式閘極無接面奈米線非揮發性記憶體並結合矽奈米晶體，來提升元件記憶窗口和可靠度。本研究所使用的矽奈米晶體製程簡單且與現今快閃記憶體製程相容性高，因此很有機會可以使用在未來記憶體元件和高密度的三維堆疊技術上。
在本研究的穿隧式(FN-tunneling)寫入/抹除機制中可以發現N 型通道有較佳的寫入效率而P型通道則有較佳的抹除效率。在可靠度分析上，經過一萬次的寫入/抹除P型元件仍有良好的特性但是N型通道卻有衰退的現象，從SS的分析中可以發現N型元件在多次寫入/抹除後產生缺陷造成寫入/抹除速度和SS的劣化。然而，在溫度85°C下模擬十年後的元件儲存電荷能力，在N型和P型都有優異的展現(大於90%)，這是由於矽奈米晶體的貢獻有較深的傳導帶和價電帶可以防止電荷流失。本研究也提出另一個使用在P型元件的抹除機制BBHH，經過一萬次的寫入/抹除測試仍然有相當優異的特性且將元件放置在溫度85°C下模擬十年後的元件儲存電荷能力，也有超過90%的電荷儲存；經由以上的兩種機制可以了解具環繞式閘極無接面奈米線非揮發性記憶體並結合矽奈米晶體元件，不只提升寫入/抹除效率也有優異的可靠度特性。

In this study, we demonstrated the Gate-All-Around Junctionless FinFET SOncOS Nonvolatile Memory with Silicon Nanocrystals to improve the memory window and reliability. Moreover, the Si-NCs has the simple process and compatible with current Flash memory process. Therefore, it has more opportunity to apply for high density 3D stack technology.
In this research, the n-channel device has better programming efficiency and p-channel device has better erasing efficiency by using the FN-tunneling mechanisms. In the reliability analysis, the p-channel device has excellent P/E cycles but the n-channel device is degenerative. For n-channel device, the interface traps lead to the SS degeneracy and reduce the P/E speed. However, the n-channel and p-channel devices have good retention characteristic during the 85°C to simulate the ability of retaining charges after ten years. The good retention ability is contributed which Si-NCs has the deep conduction and valence band to store the charge. On the other hand, we proposed the BBHH erase mechanism in p-channel device. After the 104 P/E cycles it still has excellent characteristic. For retention characteristic, the device memory windows maintain more 90% under ten years at 85°C. Above the mention, we can realize the Gate-All-Around Junctionless FinFET SOncOS Nonvolatile Memory with Silicon Nanocrystals device not only enhance the P/E efficiency but also improve the reliability.

中 文 摘 要 i
Abstract ii
Acknowledge iv
Contents vi
Figure Captions viii
Chapter 1 1
Introduction 1
1.1 Introduction of Junctionless Device 1
1.2 Introduction to Nonvolatile Memory 5
1.3 The SONOS NVM 8
1.4 The 3D stack of poly-Si channel 10
1.5 Motivation 12
1.6 Thesis Organization 15
Chapter 2 16
Basic Mechanism and Reliability of Nonvolatile Memory 16
2.1 Introduction 16
2.2 Basic Mechanisms 18
2.2.1 Fowler-Nordheim (FN) Tunneling 18
2.2.2 Channel Hot-Electron Injection (CHEI) 21
2.2.3 Band-To-Band Tunneling induced Hot-Electron 23
2.2.4 Band-To-Band Tunneling induced Hot-Hole 28
2.2.5 Fowler-Nordheim (FN) Tunneling erase 30
2.3 Reliability 31
2.3.1 Endurance 31
2.3.2 Retention 31
Chapter 3 32
Device Fabrication and Simulation 32
3.1 Device structure and fabrication 32
3.2 Simulation of GAA Structure 34
Chapter 4 36
Characteristics of Gate-All-Around SONOS Nonvolatile Memory with Silicon Nanocrystal 36
4.1 TEM and SEM Image Analysis 36
4.2 FN-Tunneling Programming 41
4.2.1 Id-Vg Characteristic 41
4.2.2 Program/Erase Characteristic 42
4.2.3 Endurance Characteristic 46
4.2.4 Retention Characteristic 48
4.3 Band-To-Band Tunneling Induced Hot Hole (BBHH) Injection Erasing 51
4.3.1 Program/Erase Characteristic and Simulation 51
4.3.2 Endurance Characteristic 54
4.3.3 Retention Characteristic 55
4.4 Channel Hot-Electron Injection (CHE) program 56
4.5 Band-To-Band Tunneling Induced Hot Electron (BBHE) Injection program 58
Chapter 5 60
Conclusion 60
Reference 62

Chapter 1
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Chapter 2
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Chapter 3
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