無接面薄膜電晶體為一種未來可行的元件，因其製程簡單、熱預算少、短通道效應不明顯等優點。但由於無接面式電晶體需做成薄膜型態才能將通道關上，此原因使得無接面式薄膜電晶體的飽和電流受到壓制，呈現小電流的情況。此篇論文提出升抬式汲源極結合無接面式薄膜電晶體，藉此降低串聯電阻，使得飽和電流升高。在基本電性上，汲源極抬升使得無接面薄膜晶體的飽和電流能達到1μA 比起之前文獻高出快十倍。使用抬升式汲源極結構可保留原本無接面電晶體薄通道的特性，其基本電性如SS將近100mV/dec.;漏電流低至10-14A，因此使用升抬式汲源極可整合博通到結構，進而使得元件特性提升。
在可靠度分析中，我們將有升抬式汲源極的無接面電晶體施予加熱分析，從基本電性圖中，看出重要參數的變化如:SS，Vth，Ion ，Ioff ，藉此分析元件的熱穩定性，以及與溫度的相依姓，值得一提的是我們以多晶矽做出來的元件，在Vth隨溫度的飄動上，與單晶的元件行為類似。對於stress的實驗中，在匝極施予固定的偏壓，看元件在連續偏壓下裂化的程度。比較P型與N型元件，可發現在此種stress條件下，N型元件相較於P型元件抗stress.
在升抬式汲源極無接面電晶體中，我們應用了雙匝極(Dual Gate)的概念，在同一層中，我們同時定義出兩條匝極，控制同一條通道，此種元件在操作時發現藉由兩條匝極施予不同的電壓條件，元件的Vth可做彈性的調變，對於邏輯元件而言，這是一個很好的應用。在此篇研究中，討論了操作電壓與元件電性的變化。
此篇研究中，成功做出一種新穎的無接面電晶體。由於無接面電晶體需要做薄才能運作，但薄化的製程不易控制，因此本篇提出利用”bulk”元件的概念，做出混合式反參雜通道的薄膜電晶體，藉著不同參雜，產生空乏區，使等效通道變薄。基本的結構圖、電性圖與模擬圖將會在內文中提及與討論。

The junctionless transistor is proposed to be a future device because of the simple fabrication and suffered the suppression of On-current owing to the thin channel structure. The raised source and drain (RSD) structure is combined with the juncitonless transistor for the improvement of On-current. In the basic electrical measurement, the On-current of the RSD device almost reaches 1μA that is ten times for that of the non-RSD devices. The RSD juncitonless device gets the steep sub-threshold swing (SS=100mV/dec.) and the Off-current is low (10-14A) due to the remained thin channel structure.
For reliability experiment, the temperature and the stress tests are taken for the RSD junctionless device. When the RSD junciotnlees device is heated up, the positive shifting of threshold voltage, degradation of SS and increase of the On-current as well as Off-current could be observed. The stress operation makes the electrical characteristics of the RSD junciotnless device changes due to the trapped carriers injected by gate at the edges of the gate insulator.
The special structure of the N-type RSD juncitonless device called the dual gate is discussed. The two gates at the same layer would make the threshold voltage become tunable flexibly. For the N-type RSD juncitonless device, when the bias-gate voltage is negative, the Vth would shift toward the right side. When the bias gate voltage is positive, the Vth would shift toward the left side. It should be noticed that the shifts of Vth is linear regression with the bias gate voltage as well as the change of the On-current fits the quadratic regression.
The new structure of the junctionless device is brought up called Hybrid P/N channel. The idea of the Hybrid P/N channel is intrigued by the bulk device. The different type layers are stacked as the channel to enhance the simplicity of the fabrication for the thin channel. The performance of the Hybrid P/N is good with the low SS (89mV/dec.). The simulation is added for proving the existence of the depeletion region.

中 文 摘 要 I
Abstract III
Acknowledge V
Contents IX
Figure Captions XI
Chapter 1 1
Introduction 1
1-1 Introduction of Junctionless Device 1
1-2 Thesis Organization 6
Chapter 2 8
Junctionless Device and Motivation 8
2-1 Basic Design Guideline of Junctionless Transistor 8
2-2 Junctionless Mechanism 11
2-3 Motivation for Raised S/D device 15
2-4 Motivation for Hybrid P/N JL device 17
Chapter 3 19
Device Fabrication 19
3-1RSD JL-TFT Device Fabrication Process 19
3-1Hybrid P/N JL Device Fabrication Process 21
Chapter 4 23
RSD Device Characteristics Analysis 23
4-1 RSD JL-TFT Device 23
4-1-1.TEM and 3D images Analysis 23
4-1-2. Device Electrical Analysis 24
4-1-3. Conclusion 29
4-2 Temperature Reliability Test 30
4-2-1 Introduction 30
4-2-2 Result and Discussion 31
4-2-3 Conclusion 34
4-3 Stress Reliability Test 35
4-3-1 Introduction 35
4-3-2 Result and Discussion 36
4-3-3 Conclusion 42
4-4 RSD Dual-Gate Device Characteristics 43
4-4-1 Introduction 43
4-4-2 Result and Discussion 44
4-4-3 Conclusion 53
Chapter 5 54
Hybrid P/N device Characteristics 54
5-1 Introduction 54
5-2 Result and Discussion 55
5-3 Conclusion 59
Chapter 6 60
Conclusion 60
Reference 63

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