本論文要實作迭代式低密度奇偶檢查碼編碼調變系統的硬體，迭代式系統的解調器將收到的符元和解碼器的軟性回饋值算出外來訊息當作是解碼器的先驗概率，而解碼器經過一次內部迭代後會得到更新後的後驗概率，後驗概率減去先驗概率得到新的軟性回饋值，此為一次外部迭代，迭代式系統通過解調器和解碼器交換訊息來更正資料框。我們在解調器部分提出三種近似方法，在沒有太多性能下降的情形下簡化解調器的運算；解碼器部分使用分層式解碼架構，解碼演算法則為最小值-總合演算法。而為了提升系統吞吐量，我們讓兩筆資料框能同時在系統中輪流使用解調器和解碼器，不過每個資料框會需要有自己的記憶體儲存上一次外部迭代的值，所以像是變數節點正負號記憶體、檢查節點記憶體、先驗概率記憶體和外來訊息記憶體都需要增加一塊記憶體面積，不過我們可以協調解調器和解碼器的排程，使得在不會有記憶體存取衝突的情形下，將兩筆資料框的值放在同一塊記憶體中，如此能減少記憶體面積和控制器的複雜度。最後和傳統的非迭代式系統做比較，能得到較好的吞吐量-面積比值。

This thesis is to implement hardware design of LDPC coded modulation with iterative demodulator and decoding system. Demodulator and decoder exchange information in iterative demodulator and decoding system to increase performance of LDPC coded modulation system. For hardware of demodulator, we proposed three approxmate methods to reduce hardware complexity of demodulator without significantly performance loss. Moreover, we lower the number of symbols simultaneously processed in demodulator to avoid unnecessary area increase. We adopt new layered decoding architecture compatible to our system to finish our LDPC decoder. To improve system throughput, two frames are in iterative demodulator and decoding system, and use hardware resource of demodulator and decoder by turns. Consequently, we achieve better throughput and throughput-area ratio(TAR) compared to non-iterative demodulator and decoding system.

1 簡介 1
2 回顧 4
2.1 低密度奇偶檢查碼........................4
2.2 非迭代式低密度奇偶檢查碼編碼調變...........6
2.3 迭代式低密度奇偶檢查碼編碼調變.............7
3. 迭代式低密度奇偶檢查碼編碼調變硬體設計 10
3.1 適用於硬體實作之8-ASK解調器..............10
3.2 8-ASK解調器之硬體架構...................18
3.3 分層式低密度奇偶檢查碼硬體架構.............22
3.4 迭代式解調解碼系統硬體實現................25
4 模擬與實作結果 29
4.1 模擬結果..............................29
4.2 迭代式與非迭代式系統系統合成結果..........32
4.2.1 迭代式系統......................32
4.2.2 非迭代式系統.....................35
4.2.2 迭代式系統與非迭代式系統綜合比較.....39
4.3 自動化佈局結果..........................40
5 結論 43

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