在NAND快閃記憶體發展歷史當中，由更高的密度來降低晶片成本一直是驅動此一技術演變的主要動力。以傳統平面式NAND快閃記憶體而言，當關鍵尺寸(Critical Dimension, CD)微縮到十奈米時，持續劣化的晶胞(cell)元件特性以及自對準四重圖案(Self Aligned Quadruple Patterning, SAQP)製程將會是此技術開發的主要挑戰。為了能持續追求更具競爭力的NAND快閃記憶體，近年來，三維NAND快閃記憶體技術發展迅速。由於三維NAND記憶體可以採用較大的晶胞尺寸來改善晶胞元件特性，而且利用所謂的”多重堆疊一次蝕刻”的概念，可以得到更低的位元成本(bit-cost)。因此，有別於傳統NAND快閃記憶體技術僅在平面方向上的微縮，三維NAND快閃記憶體將多層記憶體垂直堆疊起來，再利用一次性的深蝕刻獨立出各個單位晶胞，以達到更佳的元件表現和更具競爭力的生產成本，進而讓NAND快閃記憶體技術持續微縮下去且同時符合經濟效益。
在眾多三維NAND快閃記憶體當中，每種架構都有各自的優缺點。首先，本研究先針對不同架構進行評估發現，採用水平電流流動方式的垂直閘極(Vertical Gate, VG)形式三維NAND快閃記憶體除了微縮平面關鍵尺寸佔有優勢之外，其架構的讀取電流也不因堆疊層數增加而降低。因此，本研究選定以垂直閘極形式架構為主軸，並針對此架構衍生的特殊效應進行一系列的分析以及優化。在本研究的第二章將介紹垂直閘極形式三維NAND快閃記憶體的設計與結構，包含其操作與選取晶胞之方法。
本論文第三章先探討垂直閘極形式三維NAND的陣列效率(array efficiency)，並藉由改變晶胞串(NAND string)的架構來提高平面的陣列效率，本章中先回顧Chen等人先前提出的”分割頁”(split-page)架構以及其陣列效率，接著本章再提出交錯狀閘極(stagger gate)的新架構來減少串選擇線(string select line, SSL)佔據陣列的比例，此新架構可以將原本只有71%的陣列效率提升至81%。此外，此研究也針對這種新的串選擇線架構的操作方式和電性表現作一詳盡的探討，提供日後能設計出更具成本競爭力的垂直閘極形式三維NAND快閃記憶體。
在三維記憶體製程當中，一次性的深蝕刻必須確保所有晶胞能夠被獨立分離，關鍵的製程能力就是其蝕刻機台所能達到的最大深寬比值(Aspect Ratio)，因此，在不改變蝕刻製程能力的前提下，進一步微縮每一層薄膜的厚度將會得到更高的記憶體密度。本研究第四章利用2層架構的元件進行垂直間距(Z-pitch)的微縮實驗。研究中發現，雖然實驗成功將垂直間距從60奈米縮小到18奈米，但卻也遭遇到記憶容限度(memory margin)衰退以及讀取電流降低的問題。對於記憶容限度衰退的機制，垂直干擾(Z-interference)以及垂直擾動(Z-disturbance)等兩種不同機制能夠完整解釋抑制電晶體(inhibited transistor)的臨限電壓(threshold voltage)之改變，其中又以垂直干擾為主要影響記憶容限度的機制，本論文將在第五章更深入地研究垂直干擾，實際量測8層結構的元件，輔以模擬的結果提出一組合適的垂直間距當作基準，並進一步探討如何減少垂直干擾以及增加記憶容限度的可行方法。
除了垂直間距會直接改變元件特性之外，水平方向上的距離也同樣對元件有重要影響。其中，一個重要的參數是邊緣字元線(edge word line)到接地選擇線(ground select line, GSL)或到串選擇線(SSL)的距離，第六章探討此距離大小對於垂直閘極形式三維NAND陣列在操作上的影響，包含讀取電流(sensing current)，寫入抑制(programming inhibition)，以及刪除速度(erasing speed)等電性差異，透過實驗和模擬的結果也歸納出最適合的距離作為此架構之設計準則。
最後，在第七章根據前面的主題以及結果，整理出垂直閘極形式三維NAND快閃記憶體在製作上以及設計上的重要準則，同時間，藉由此研究過程也將更加了解此技術的優勢以及其限制。

Throughout the technology development history of NAND Flash memory, the lower chip cost achieved by higher density array is the main driving force for further evolution. For conventional planar 2D NAND, when the critical dimension (CD) is shrunk to 10nm node, it will inevitably encounter numerous challenges in terms of degraded device performance and complex process modules, such as SAQP (Self-Aligned Quadruple Patterning) scheme. In order to keep pursuing more competitive NAND Flash memory, 3D (three dimensional) NAND Flash technology has been rapidly developed in recent years. 3D NAND Flash memory can improve the device performance by designing a larger cell size. Moreover, it can also achieve lower bit-cost based on the concept of “multiple-layer stack and one critical etching”. Unlike the cell size is relentlessly shrunk in the conventional NAND technology, the 3D NAND Flash memory stacks plural memory layers with relaxed cell size and divides each device by a deep etching scheme, which makes it as a high performance and low cost chip. Via this concept, NAND technology could be effectively scaled in an economic way.
Among the 3D NAND Flash architectures ever proposed, each one owns its merits and demerits. After systematic comparison, it is found that the Vertical Gate (VG) type 3D NAND architecture possesses the superiority of smaller cell size than that of Vertical Channel (VC) one. Besides, the sensing current of this architecture will not be degraded when stacking more layers vertically. Therefore, this work analyzes and optimizes the special effects encountered inherently in the VG-type 3D NAND architecture. In Chapter 2, the VG-type 3D NAND array design and structure will be introduced. Furthermore, the corresponding operations and the decoding methods are also revealed in Chapter 2.
As to Chapter 3, the “split-page” architecture that previously proposed by Chen et al., will be reviewed and its array efficiency will be discussed. Then we will propose a new string decoding scheme, named stagger string select line (stagger SSL) scheme, to improve the array efficiency from 71% to 81%. The corresponding operations and electrical data of this scheme will also be studied therein. Stagger SSL scheme is a promising method for cost-effective design of VG-type 3D NAND architecture in the future.
In 3D NAND process, the process capability of the critical etching module is limited by the highest aspect ratio (AR) that could be achieved by the etching tool. Thus, for a given stack height, we will obtain a higher array capacity by scaling down the thickness of each memory layer. In Chapter 4, the Z-pitch (one poly-silicon and one oxide) reduced from 60nm to 18nm were successfully demonstrated by using two-layer devices. However, the memory margin and read current are degraded accordingly when shrinking the Z-pitch. As to the mechanisms of memory margin degradation, both “Z-interference” and “Z-disturbance” are introduced to explain the Vt (threshold voltage) shift of inhibited transistor. Among them, Z-interference is the major killer of memory margin. Hence, the Z-interference is analyzed in detail in Chapter 5 by eight-layer devices. Aided by simulation verification, the experimental data are analyzed to propose a suitable Z-pitch as the baseline for fabricating VG-type 3D NAND. In addition, several approaches are discussed to suppress the Z-interference and enlarge the memory margin.
Not only the Z-pitch factor but also the horizontal distances can directly affect the device performances. Among various horizontal distances, one important parameter is the distance between edge word line (WL) and ground select line (GSL) or string select line (SSL) transistors. In Chapter 6, the distance effect on VG-type 3D NAND array operations, including read current, erase speed, and programming inhibition performance are discussed. Based on experimental and simulation data, the suitable distance will be summarized as a design guideline in the end of Chapter 6.
Finally, we will conclude the results from Chapters 3 to 6 to provide important guidelines on the perspectives of fabrication aspect and design aspect. Through these studies, we can well understand its merits and limitations of VG-type 3D NAND architecture.

Abstract (Chinese)………………………………………………………i
Abstract (English)……………………………………………………iv
Acknowledgement……………………………………vii
Content .…………………………………………………xi
Table Titles ......………………………………………………xv
Chapter 1 Introduction ………………………………………………1
1.1 Overview of Non-Volatile Memory technologies and Flash Memory ……1
1.2 Challenges of Scaling Planar 2D NAND Flash……3
1.3 Roadmap of 2D and 3D NAND Flash Memories…………………4
1.4 Bit-Cost Scalable Concept of 3D NAND Flash…………5
1.5 Motivation……………7
1.6 Organization of this Dissertation………8
Chapter 2 Review of VG-type 3D NAND Flash Memory…………………19
2.1 3D NAND Technologies……………………………………………19
2.2 Architecture of VG-type 3D NAND Array…………………………………21
2.3 Storage Layers of VG-type 3D NAND Array………22
2.4 Process Flow of VG-type 3D NAND Array……23
2.4.1 Minimal Incremental Layer Cost for Staircase Interconnections................23
2.4.2 Bit-line (BL) and Word-line (WL) Formation............................25
2.5 Operation Conditions of VG-type 3D NAND.................................26
2.5.1 Program Operation of VG-type 3D NAND array……………26
2.5.2 Erase Operation of VG-type 3D NAND array………………27
2.5.3 Read Operation of VG-type 3D NAND array……………29
Chapter 3 String Select Line (SSL) Decoding Scheme...........................41
3.1 Split-page Decoding Scheme Using Island-gate SSL Device...........................41
3.2 Concept of Stagger SSL Decoding Scheme................................ 42
3.3 Process Flow and BEOL Routing of Stagger SSL Decoding Scheme.......................43
3.4 Electric Performance of Stagger SSL Decoding Scheme......................................... 45
Chapter 4 Study of the Z-pitch Scaling Effect by Using a Two-layer VG-type 3D NAND Array………63
4.1 Two-layer Array for Scaling Z-pitch Study……………………63
4.2 Process Flow of Fabricating Ultra-thin PL Channels.....63
4.3 Thickness Effect on Device Performances..........................65
4.3.1 PL Thickness Effect on Read Current...........................65
4.3.2 PL Thickness Effect on Threshold Voltage.....................66
4.3.3 PL/OX Thickness Effect on Program Speed..........................67
4.3.4 PL/OX Thickness Effect on Erase Speed..........................68
4.4 Program-inhibit on Devices with Different PL or OX Thicknesses...........................68
4.5 Z-interference and Z-disturbance of Inhibited Cell Devices.......................................70
4.5.1 Z-interference………………………………………………………………70
4.5.2 Z-disturbance………………………………………………………………71
4.6 Memory Window and Z-pitches..................73
4.7 Summary of Z-pitch Scaling Effect............74
Chapter 5 Z-interference Study by Using an Eight-layer VG-type 3D NAND Array............................95
5.1 Interferences in VG-type 3D NAND Array...............................95
5.2 One-side and Two-side Z-interference............96
5.3 Z-extension of Trapped Charges..... ........97
5.4 Thickness/Critical Dimension Effects on Z-interference...98
5.4.1 PL Thickness Effect ..............98
5.4.2 OX Thickness Effect…………………99
5.4.3 Bit-line and Word-line Critical Dimension Effect ……………100
5.5 New Schemes for Improving Z-interference.......101
5.5.1 Dielectric Constant Effect ..........101
5.5.2 Gate Shape Engineering ..............102
5.6 Correlation Between Z-interference and Memory Window......................................104
5.7 Summary of Z-interference Study.................105
Chapter 6 Effect of WL to SSL/GSL Distance….......................125
6.1 Effect of WL to SSL/GSL Distance on Read Current……………125
6.1.1 Two-transistor Device for Collecting Read Current……………………125
6.1.2 Back-gate Effect for Improving Read Current……………………………126
6.1.3 Grain Boundary Traps Effect and Simulation of Read Current........ ........128
6.2 Effect of WL to SSL/GSL Distance on Self-boosting Behavior........................130
6.3 Effect of WL to SSL /GSL Distance on Erase Speed.........................133
6.4 Summary of Edge WL to SSL/GSL Distance Effect…………135
Chapter 7 Conclusions and Future Works............156
7.1 Conclusions....................156
7.2 Future Works...................158
References..............160
Vita....................173
Publication List.............................175

[1] S. Yamazaki, “History and Future Perspective of Nonvolatile Memory,” in 16th IEEE International Symposium on Applications of Ferroelectrics, pp.1-3, 2007.
[2] R. H. Dennard, "Field-Effect Transistor Memory," US patent 3387286, 1968.
[3] K. Hahng, S. M. Sze,” A floating gate and its application to memory devices,” Trans. Electron Device, vol. 14, pp. 629, Sep. 1967.
[4] B. D. Frohman, “Floating gate transistor and method for charging and discharging same,” US patent 3660819, 1970.
[5] E. Harari, “Electrically erasable non-volatile Semiconductor memory,” US patent 4115914, 1977.
[6] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, “A new flash E2PROM cell using triple polysilicon technology,” in IEDM Tech. Dig., Dec. 1984, pp. 464-467.
[7] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structure cell,” in IEDM Tech. Dig., Dec. 1987, pp. 552-555.
[8] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” in PROCEEDINGS OF THE IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
[9] M. Park, K. Kim, J. H. Park, and J. H. Choi, “Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of NAND Flash Cell Arrays,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 174-177, 2008.
[10] G. Kong, T. Kim, W. Xi, and S. Choi, “Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory,” in APMRC, 2012, pp. 1-5.
[11] K. T. Park, M. Kang, D. Kim, S. W. Hwang, B. Y. Choi, Y. T. Lee, C. Kim, and K. Kim, “A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 919-928, 2008.
[12] T. Kim, G. Kong, W. Xi, and S. Choi, “Cell-to-Cell Interference Compensation Schemes Using Reduced Symbol Pattern of Interfering Cells for MLC NAND Flash Memory,” IEEE Trans. Magnetics, vol. 49, no. 6, pp. 2569-2573, 2013.
[13] K. Prall, and K. Parat, “25nm 64Gb MLC NAND technology and scaling challenges,” in IEDM Tech. Dig., Dec. 2010, pp. 5.2.1-5.2.4.
[14] Z. S. Wang, W. S. Huang, C. Y. Chen, H. Arakawa, and C. J. Lin, “Improvement of Bottom Oxide Thickness Scaling of Inter-Poly Dielectric by Floating Gate Top Plasma Nitridation,” in IEEE Electron Device Lett., vol. 30, no. 2, pp. 190-192, 2013
[15] J. D. Lee, J. H. Choi, D. Park, and K. Kim, “Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90nm NAND flash memory cells,” in Proc. IRPS, 2003, pp. 497-501.
[16] J. Om, E. Choi, S. Kim, H. Lee, Y. Kim, H. Chang, S. Park, and G. Bae, “The effect of mechanical stress from stopping nitride to the reliability of tunnel oxide and data retention characteristics of NAND FLASH memory,” in Proc. IRPS, 2005 pp. 257-259.
[17] G. S. Kar, L. Breuil, P. Blomme, H. Hody, S. Locorotondo, N. Jossart, O. Richard, H. Bender, G. Van den Bosch, I. Debusschere, and J. Van Houdt, “Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology,” in IEDM Tech. Dig., Dec. 2012, pp. 2.2.1-2.2.4.
[18] N. Ramaswamy, T. Graettinger, G. Puzzilli, H. Liu, K. Prall, S. Gowda, A. Furnemont, C. Kim, and K. Parat, “Engineering a planar NAND cell scalable to 20nm and beyond, ” in Proc. IMW, 2013, pp. 5-8.
[19] Y. Koh, “NAND Flash Scaling Beyond 20nm,” in Proc. IMW, 2009, pp. 1-3.
[20] A. Goda, “Recent progress and future directions in NAND Flash scaling,” in Proc. 13th NVMTS, 2013, pp. 1-4.
[21] Y. Park, J. Lee, S. S. Cho, G. Jin, and E. Jung, “Scaling and Reliability of NAND Flash Devices,” in Proc. IRPS, 2014, pp. 2E.1.1-2E.1.4.
[22] A. Goda, and K. Parat, “Scaling Directions for 2D and 3D NAND Cells,” in IEDM Tech. Dig., Dec. 2012, pp. 2.1.1-2.1.4.
[23] J. Hwang, et al., “A Middle-1X nm NAND Flash Memory Cell (M1X-NAND) with Highly Manufacturable Integration Technologies,” in IEDM Tech. Dig., Dec. 2011, pp. 199-202.
[24] C. H. Lee, et al., “Channel coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node,” in Proc. IMW, 2013, pp. 72–75.
[25] K. Kim, et al., “Extending the DRAM and FLASH memory technologies to 10nm and beyond,” in Proc. of SPIE, vol. 8326, 2012, pp. 832605-1-832605-11.
[26] C. Y. Lu, K. Y. Hsieh, and R. Liu, "Future challenges of flash memory technologies," Microelectronic Engineering, vol. 86, pp. 283–286, 2009.
[27] http://www.itrs2.net/
[28] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang ; L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” in IEDM Tech. Dig., Dec. 2006, pp. 41-44.
[29] S. M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M. S. Song, K. H. Kim, J. S. Lim, and K. Kim, “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” in IEDM Tech. Dig., Dec. 2006, pp. 37-40.
[30] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in VLSI Symp. Tech. Dig., Jun. 2007, pp. 14-15.
[31] K. T. Park, D. S. Byeon, and D. H. Kim, "A World’s First Product of Three-Dimensional Vertical NAND Flash Memory and Beyond," in Non-Volatile Memory Tech. Symp., 2014, pp. 1–5.
[32] W. Jeong, et al., “A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 204-212, 2016.
[33] K. Parat and C. Dennison, “A Floating Gate Based 3D NAND Technology With CMOS Under Array,” in IEDM Tech. Dig., Dec. 2015, pp. 48-51.
[34] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama, “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices,” in VLSI Symp. Tech. Dig., Jun. 2009, pp. 136–137.
[35] J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J. H. Jeong, B. K. Son, D. W. Kim, K. Kim, J. J. Shim, J. S. Lim, K. H. Kim, S. Y. Yi, J. Y. Lim, D. Chung, H. C. Moon, S. Hwang, J.W. Lee, Y. H. Son, U. I. Chung, and W. S. Lee,“Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” in VLSI Symp. Tech. Dig., Jun. 2009, pp. 192–193.
[36] E. S. Choi, H. S. Yoo, H. S. Joo, G. S. Cho, S. K. Park, and S. K. Lee, “A Novel 3D Cell Array Architecture for Terra-bit NAND Flash Memory”, in Proc. IMW, 2011, pp. 57–60.
[37] W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, “Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage,” in VLSI Symp. Tech. Dig., Jun. 2009, pp. 188–189.
[38] H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., Jun. 2010, pp. 131–132.
[39] C. H. Hung, H. T. Lue, K. P. Chang, C. P. Chen, Y. H. Hsiao, S. H. Chen, Y. H. Shih, K. Y. Hsieh, M. Yang, J. Lee, S. Y. Wang, T. Yang, K. C. Chen, and C. Y. Lu, “A Highly Scalable Vertical Gate (VG) 3D NAND Flash with Robust Program Disturb Immunity Using a Novel PN Diode Decoding Structure,” in Symp. VLSI Technol. Dig., 2011, pp. 68–69.
[40] J. G. Yun, et al., “Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory,” in IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1006–1014, Jan. 2011.
[41] Y. Kim, J. G. Yun, S. H. Park, W. Kim, J. Y. Seo, M. Kang, K. C. Ryoo, J. H. Oh, J. H. Lee, H. Shin, and B. G. Park, “Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline Stacked Array,” in IEEE Trans. Electron Devices, vol. 59, no. 1, pp. 35–45, Jan. 2012.
[42] A. Hubert, et al., “A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration,” in IEDM Tech. Dig., Dec. 2009, pp. 637-640.
[43] H. T. Lue, Y. H. Hsiao, P. Y. Du, S. C. Lai, T. H. Hsu, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, C. P. Lu, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance,” in VLSI Symp. Tech. Dig., Jun. 2009, pp. 224-225.
[44] H. T. Lue, et al., “A Critical Review of Charge-Trapping NAND Flash Devices,” in International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2008, pp. 807–810.
[45] K. P. Chang, et al., “Effect of Junction Engineering for 38nm BE-SONOS Charge-Trapping NAND Flash Device,” in VLSI Technology, Systems, and Applications, 2011, pp. 1-2.
[46] M. White, “On the go with SONOS”, IEEE Circuits and Designs, 2000, pp. 22-31.
[47] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Lett., pp. 543-545, 2000.
[48] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pang and C. Y. Lu, “Data retention of SONOS-type two-bit storage flash memory cell”, in Proc. IEEE IEDM Tech. Dig., 2001, pp. 719-722.
[49] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” in Proc. IEEE IEDM Tech. Dig., 2005, pp. 547–550.
[50] S. H. Chen, H. T. Lue, Y. H. Shih, C. F. Chen, T. H. Hsu, Y. R. Chen, Y. H. Hsiao, S. C. Huang, K. P. Chang, C. C. Hsieh, G. R. Lee, A. T. H. Chuang, C. W. Hu, C. J. Chiu, L. Y. Lin, H. J. Lee, F. N. Tsai, C. C. Yang, T. Yang, and C. Y. Lu, “A Highly Scalable 8-Layer Vertical Gate 3D NAND With Split-Page Bit Line Layout and Efficient Binary-Sum MiLC (Minimal Incremental Layer Cost) Staircase Contacts,” in Proc. IEEE IEDM Tech. Dig., 2012, pp. 21–24.
[51] K. P. Chang, H. T. Lue, C. P. Chen, C. F. Chen, Y. R. Chen, Y. H. Hsiao, C. C. Hsieh, Y. H. Shih, T. Yang, K. C. Chen, C. H. Hung, and C. Y. Lu, “Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of It’s Program Inhibit Characteristics,” in Proc. IMW, 2012, pp. 1–4.
[52] T. H. Yeh, et al., “Gate stack etch induced reliability issues in nitrided-based trapping storage cells” in VLSI Technology, Systems, and Applications, 2010, pp. 48-49.
[53] W. C. Chen, et al., “Study of the Programming Sequence Induced Back-Pattern Effect in Split-Page 3D Vertical-Gate (VG) NAND Flash” in VLSI Technology, Systems, and Applications, 2014, pp. 45-46.
[54] H. Aochi, et al., “Three Dimensional Flash Memory with Bit Cost Scalable Technology for the Future Ultra High Density Storage Devices” in International Conference on Solid State Devices and Materials, 2008, pp. 820-821.
[55] Y. Komori, et al., “Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device,” in Proc. IEEE IEDM Tech. Dig., 2008, pp. 851–854.
[56] H. T. Lue, K. P. Chang, C. P. Chen, T. H. Yeh, T. H. Hsu, P. Y. Du, Y. H. Shih, and C. Y. Lu, “A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming,” in VLSI Symp. Tech. Dig., Jun. 2013, pp. 152-153.
[57] H. T. Lue, P. Y. Du, W. C. Chen, T. H. Yeh, K. P. Chang, Y. H. Hsiao, Y. H. Shih, C. H. Hung, and C. Y. Lu, “A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space,” in Proc. IEEE IEDM Tech. Dig., 2013, pp. 80–83.
[58] T. Krishnamohan, et al., “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60mV/dec Subthreshold Slope,” in Proc. IEEE IEDM Tech. Dig., 2008, pp. 947–949.
[59] H. T. Lue, T. H. Yeh, K. P. Chang, T. H. Hsu, Y. H. Shih, and C. Y. Lu, “A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory,” in VLSI Symp. Tech. Dig., Jun. 2014, pp. 158-159.
[60] T. H. Yeh, C. J. Wu, C. W. Hu, W. C. Chen, H. T. Lue, Y. H. Shih, Y. C. King, and C. Y. Lu, “A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-type) 3D NAND,” in IEEE Electron Device Lett., pp. 330-332, 2015.
[61] Y. R. Chen, C. J. Wu, K. P. Chang, C. P. Chen, T. H. Hsu, Y. H. Hsiao, F. N. Tsai, Mars Yang, Y. D. Huang, L. Y. Lin, T. Yang, C. J. Chiou, S. H. Chen, H. T. Lue, Y. H. Shih, and C. Y. Lu, “Trapping-free String Select Transistors and Ground Select,” in Proc. IMW, 2014, pp.119-122.
[62] H. H. Hsu, T. W. Liu, L. Chan, C. D. Lin, T. Y. Huang, and H. C. Lin, “Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations,” in IEEE Trans. Electron Devices, vol.55, no.11, pp. 3063-3069, Nov. 2008.
[63] H. C. Lin, W. C. Chen, C. D. Lin, and T. Y. Huang, “Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness,” in IEEE Electron Device Lett., vol. 30, no. 6, pp. 644-646, 2009
[64] P. Y. Du, H. T. Lue, Y. H. Shih, K. Y. Hsieh, and C. Y. Lu, “Overview of 3D NAND Flash and Progress of Split-Page 3D Vertical Gate (3DVG) NAND Architecture,” in International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014, pp. 1–4.
[65] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, H. M. Choi, K. H. Hwang, Y. Ko, and C. J. Kang, “Investigation of Ultra Thin Polycrystalline Silicon Channel for Vertical NAND Flash,” in Proc. IEEE IRPS, 2011, pp. 126-129.
[66] T. H. Yeh, P. Y. Du, T. H. Hsu, W. C. Chen, H. T. Lue, Y. H. Shih, Y. D. Huang, H. H. Hsu, L. Y. Lin, Y. C. King, T. Yang, and C. Y. Lu, “Increasing VG-Type 3D NAND Flash Cell Density by Using Ultra-Thin Poly-Silicon Channels,” in Proc. IMW, 2013, pp. 139–142.
[67] T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, L. W. Yang, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET,” in Proc. IEEE IEDM Tech. Dig., 2007, pp.913-916.
[68] M. Lenzinger, E. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2, ” in J. Appl. Phys., 40: 1969, pp. 278-283.
[69] W. C. Chen, H. T. Lue, Y. H. Hsiao, T. H. Hsu, X. W. Lin, and C. Y. Lu, “Charge Storage Efficiency (CSE) Effect in Modeling the Incremental Step Pulse Programming (ISPP) in Charge-Trapping 3D NAND Flash Devices,” in Proc. IEEE IEDM Tech. Dig., 2015, pp.117-120.
[70] H. T. Lue, R. Lo, C. C. Hsieh, P. Y. Du, C. P. Chen, T. H. Hsu, K. P. Chang, Y. H. Shih, and C. Y. Lu, “A Novel Double-Trapping BE-SONOS Charge-Trapping NAND Flash Device to Overcome the Erase Saturation without Using Curvature-Induced Field Enhancement Effect or High-K (HK)/Metal Gate (MG) Materials,” in Proc. IEEE IEDM Tech. Dig., 2014, pp.498-501.
[71] C. C. Hsieh, H. T. Lue, Y. C. Li, K. P. Chang, H. C. Lu, H. P. Li, W. C. Chen, Y. H. Hsiao, S. N. Hung, T. W. Chen, Y. H. Shih, and C. Y. Lu, “Study of the Interference and Disturb Mechanisms of Split-Page 3D Vertical Gate (VG) NAND Flash and Optimized Programming Algorithms for Multi-level Cell (MLC) Storage,” in VLSI Symp. Tech. Dig., Jun. 2013, pp. 156-157.
[72] T. H. Yeh, W. C. Chen, T. H. Hsu, P. Y. Du, C. C. Hsieh, H. T. Lue, Y. H. Shih, Y. C. King, and C. Y. Lu, “Z-interference and Z-disturbance in Vertical Gate-Type 3-D NAND,” in IEEE Trans. Electron Devices, vol.63, no.3, pp. 1047-1053, Mar. 2016.
[73] H. T. Lue, E. K. Lai, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel junction-free BE-SONOS NAND flash,” in VLSI Symp. Tech. Dig., Jun. 2008, pp. 140-141.
[74] Y. H. Hsiao, H. T. Lue, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Modeling and Scaling Evaluation of Junction-Free Charge-Trapping NAND Flash Devices,” in VLSI Technology, Systems, and Applications, 2009, pp. 103-104.
[75] J. W. Han, S. W. Ryu, D. H. Kim, and Y. K. Choi, “Polysilicon Channel TFT With Separated Double-Gate for Uni?ed RAM (URAM)—Uni?ed Function for Nonvolatile SONOS Flash and High-Speed Capacitorless 1T-DRAM,” in IEEE Trans. Electron Devices, vol.57, no.3, pp. 601-607, Mar. 2010.
[76] M. Wang, and M. Wong, “An Effective Channel Mobility-Based Analytical On-Current Model for Polycrystalline Silicon Thin-Film Transistors,” in IEEE Trans. Electron Devices, vol.54, no.4, pp. 869-874, Apr. 2007.
[77] N. Gupta, and B. P. Tyagi, “Mobility Model of Polysilicon Thin-Film Transistor (Poly-Si TFT),” in International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2004, pp. 950–953.
[78] Y. H. Hsiao, H. T. Lue, W. C. Chen, K. P. Chang, Y. H. Shih, B. Y. Tsui, K. Y. Hsieh, and C. Y. Lu, “Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices,” in IEEE Trans. Electron Devices, vol. 61, no. 6, pp, 2064-2070, 2014.
[79] J. T. Sheu, P. C. Huang, T. S. Sheu, C. C. Chen, and L. A. Chen, “Characteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistors,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 139-141, 2009.
[80] E. O. Kane, “Theory of tunneling,” in Journal of Applied Physics, vol. 32, no. 1, pp. 83– 91, 1961.