現今三維積體電路已經被廣泛的研究，因為這個技術可以打破傳統二維微縮下的極限限制。自直通矽晶穿孔可有效提升IC封裝密度，是為了主流3DIC連接技術；不過直通矽晶穿孔製程需要凸塊製程(Bumping)以及達成高深寬比(Aspect Ratio)的結構，致使面臨高成本以及可靠度的問題。應用於三維積體電路之非接觸式傳輸則包括了電感耦合以及電容耦合等方式，由於非接觸式之傳輸介面擁有比較高的良率以及較低的成本，在低頻傳輸的應用下逐漸可與直通矽晶穿孔技術競爭。本論文提出一個全新的非接觸式三維積體電路傳輸概念，利用一個金屬線圈當作磁場產生器，一個磁性穿隧接面(MTJ)當作磁感應器。在此高靈敏度磁場感測元件中磁矩翻轉是非常快速而且沒有記憶特性，將其與CMOS邏輯製程下製作的傳輸端金屬線圈上結合，即可達成以磁場感測作為3DIC資料傳輸介面之單元並達到低成本以及高頻寬的特性。

Currently, 3D integrated circuits have received widespread interests, since this technology has the potential to break through the limits of traditional 2-D circuits. TSV is main stream technology since it gives rise to the high packing density and operates under low power. However, the fabrication process of TSV requires the formation of bumps and high aspect ratio structure, leading to higher cost and reliability issues. Contactless 3D IC connection, including inductive and capacitive coupling links, becomes more promising, due to its better yield and lower cost.
In this paper, a new concept of contactless 3D connection interface through magnetic field modulation is firstly reported. This data transmission module uses a micro-coil as magnetic field generator and using a MTJ structure as magnetic field sensor. Magnetic spin is high sensitive device consider to be very fast and without memory characteristic. This 3D IC technology opportunity to achieve a low cost and wide bandwidth scheme by implementing CMOS compatible MTJ as receiver, CMOS compatible micro-coil as transmitter.

摘要 1
Abstract 2
誌謝 3
內文目錄 4
附圖目錄 6
1.1研究動機 8
1.2章節介紹 8
第二章 三維系統及垂直傳輸簡介 10
2.1 三維積體電路簡介 10
2.2 堆疊結構介紹 10
2.2.1 封裝堆疊 11
2.2.2 晶片堆疊 11
2.2.3 晶圓堆疊 11
2.3 垂直傳輸技術 12
2.3.1 TSV 12
2.3.2 電容耦合技術 12
2.3.2 電感耦合技術 13
2.4 小總結 13
第三章 元件架構簡介及線圈模擬 21
3.1元件架構介紹 21
3.1.1磁感應器(MTJ) 21
3.1.2線圈基本特性 22
3.2 線圈優化及模擬 23
3.2.1單層線圈設計 24
3.2.2雙層線圈設計 24
3.3線圈及磁感應器模擬分析 25
3.4小總結 27
第四章 量測結果分析 43
4.1磁感應器特性量測結果分析 43
4.2 線圈及磁感應器特性量測結果分析 43
4.3 總結 44
第五章 結論 54
參考文獻 55

[1] E. Jan Vardaman,2003, “Developments and Trends in Stacked Die CSPs” ,IEEE International Conference on Electronic Packaging Technology, pp.145-146.
[2] Hsin-Chu Yu, “The 3rd dimension-more life for Moore’s law,” in International Microsystems Packaging Asembly Conference Taiwan, Oct. 2006, pp. 1-6.
[3] S. F. Al-Sarawi, D. Abbott, and P. D. Franzon, “A review of 3-D packaging technology,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 21, no. 1, pp. 2-14, Feb. 1998.
[4] A. Yoshida, J. Taniguchi, K. Murata, M. Kada, Y. Yamamoto, Y. Takagi, T. Notomi, and A. Fujita, “A study on package stacking process for package-on-package (PoP),” in Electronic Components and Technology Conference, Nov. 2006, pp. 6-11.
[5] Black Bryan, Annavaram Murali, Brekelbaum Ned, DeVale John, Jiang Lei, H. Loh Gabriel, McCaule Don, Morrow Pat, W. Nelson Donald, Pantuso Daniel, Reed Paul, Rupley Jeff, Shankar Sadasivan, Shen John, and Webb Clair, ”Die stacking (3D) microarchitecture,” in Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2006, pp. 469-479.
[6] J. A. Burns, B. F. Aull, C. K. Chen, Chen Chang-Lee, C. L. Keast, J. M. Knecht, V. Suntharalingam, K. Warner, P. W. Wyatt, and D. R. W. Yost, “A wafer-scale 3-D circuit integration technology,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2507-2516, Oct. 2006.
[7] J. Burns, et al., “Three-Dimensional Integrated Circuit for Low-Power, High-Bandwidth Systems on a Chip,” IEEE ISSCC Digest of Technical Papers, pp. 268-269, Feb 2001.
[8] K. Takahashi, et al., “Through Silicon Via and 3-D Wafer/Chip Stacking Technology,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 114-117, June 2006.
[9] K. Kanda, et al., “A 1.2Gb/s/pin Wireless Superconnect (WSC) Interface Scheme,” IEEE ISSCC Digest of Technical Papers, pp. 186-187, Feb. 2003.
[10] N. Miura, D. Mizoguchi, T. Sakurai, T. Kuroda, “Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect,” IEEE J. Solid-State Circuits, pp. 829-837, April 2005.
[11] R. H. Havemann, J. A. Hutchby, “High-performance interconnects: an integration overview,” in Proc. IEEE, May 2001, pp. 586-601.
[12] 李尚凡，1999， “漫談穿隧磁電阻”， 中華民國磁性技術學會會訊，Vol. 19，1卷，頁21~25。
[13] Sadamichi Maekawa, and Teruya Shinjo, 2002, SPIN DEPENDENT TRANSPORT IN MAGNETIC NANOSTRUCTURES, Taylor & Francis.
[14] Yue, C.P.; Wong, S.S., “Physical Modeling of Spiral Inductors on Silicon” , Electron Devices, IEEE Transactions on, Volume:47 Issue:3, March 2000 Page(s):560~568.