根據莫爾定律(Moore’s law)的預測下，每18個月在同樣面積的晶圓下，電晶體數量增加一倍，這代表著電路性能越來越佳、成本降低、元件尺寸向下微縮。即使到近幾年，製程技術已經相當成熟，莫爾定律依舊是適用的預測，但隨著元件尺寸從過去的0.18µm到現在發展中的10nm，所面對到的問題更趨艱難，其中一個問題就是當元件尺寸逐漸縮小時，低頻雜訊(Low Frequency Noise)對於電路的影響會更大。
過大的低頻雜訊會對Memory或是RF電路帶來不可預期的錯誤，這讓許多專家學者紛紛研究低頻雜訊的影響以及如何減少低頻雜訊，但也有人將低頻雜訊拿來應用，例如：隨機亂數產生器、類神經網路、隨機共振、溫度感測器…等等。
本論文使用的雜訊源主要是由接觸點電阻式記憶體(Contact Resistive Random Access Memory，CRRAM)內部的陷阱(trap)產生隨機電報雜訊，藉由調整RRAM元件的工作組態(HRS or LRS) ，可以調變功率比達〖10〗^4倍，更重要一點，由於雜訊產生來源主要是由接觸點電阻式記憶元件內部的陷阱產生，其製程與CMOS邏輯製程完全相容，不需額外的光罩或製程步驟，同時獲得較佳的雜訊調變效果以及面積小低成本等優點。

According to the prediction of Moore’s law, the number of components in integrated circuits double every two years. Performance betters with decreasing cost per chip for scaling down of device. It is accurate even for now. However, there are many new challenges when gate length scales from 0.18µm down to 10nm. One of the key issues is how to deal with the increasing impact of low frequency noise on scaled device.
The low frequency noise , which received more and more attention in recent years, causes the unpredictable results in memory and RF circuits. On the other hand, low frequency noise is directed to unique applications, such as random number generator, artificial neural network, stochastic resonance, and temperature detector, etc.
In this paper, we present a novel low frequency noise generator with voltage control modulation based on contact resistive random access memory (CRRAM), which has small area and full compatibility with advanced CMOS logic process. The 1/f noise and random telegraph noise(RTN) characteristics of CRRAM has been investigated for possible application as a noise generation source. An adjustable noise generator has been demonstrated to provide noise power at levels changed several decades for applications in stochastic neuromorphic computation.

內文目錄
第一章 序論
1.1 序論 1
1.2 低頻雜訊的應用 1
1.3 論文大綱 3
第二章 可調變雜訊產生器之回顧
2.1 雜訊介紹 9
2.1.1 熱雜訊(Thermal noise) 9
2.1.2 隨機電報雜訊(Random telegraph noise) 10
2.1.3 散粒雜訊(Shot noise) 10
2.2 雜訊產生器介紹 10
2.2.1 淺溝槽絕緣(STI)架構 11
2.2.2 電阻式保護氧化層(RPO)架構 12
2.2.3 數位濾波器架構…………………………………... ….12
2.2.4 SiN電晶體架構…………………… ………..........…. 12
2.3 小結 12
第三章 接觸點電阻式記憶元件分析
3.1 接觸點電阻式記憶元件的結構與操作方式 21
3.1.1 接觸點電阻式記憶元件的結構介紹 21
3.1.2 接觸點電阻式記憶元件的操作方式 22
3.2 閘極電流隨機電報雜訊 22
3.3 新型隨機亂數產生器電路架構 24
3.4 小結 24


第四章 CRRAM-based調變雜訊產生器量測結果與分析
4.1 Flicker noise量測 35
4.1.1 量測環境設置 35
4.1.2 量測流程及儀器設定 35
4.2 1/f 雜訊量測 36
4.2.1 標準MOSFET的1/f 雜訊量測結果 36
4.2.2 1T1R的1/f 雜訊量測結果 36
4.3 1T1R與標準MOSFET雜訊調變能力 37
4.3.1 閘極電壓影響雜訊功率比量測結果 37
4.3.2 汲極電壓影響雜訊功率比量測結果 37
4.4 小結 38
第五章 總結
5.1 CRRAM-based調變雜訊產生器優點分析 47
5.2 總結及未來展望 47
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