由於靜態隨機存取記憶體具有快速存取的記憶功能，因此在電子產品中是一個非常重要的電路。它的容量是影響整個系統速度的主要原因。為了達到大量存取資料的需求，此記憶體在整個系統所佔的面積越來越多。因此，降低功率消耗變成是一個非常重要的議題
為了減少靜態隨機存取記憶體的功率消耗，降低操作電壓是一個有效的方法。然而靜態隨機存取記憶體於低電壓操作將面臨以下問題: (1) 於讀取操作產生讀取失真 (2) 於寫入操作產生半選擇失真 (3) 於寫入操作產生寫入失敗。過去的作品提出一個新穎的記憶胞搭配雙相分離控制電路。此記憶胞的字組線被分成字組線1與字組線2。其特色為單邊寫入於兩個相位中並且單邊讀出於一個相位中。此記憶胞藉由抬高地端的電壓以改善讀取失真。然而，根據記憶胞的佈局，其面臨接地彈跳的問題。因此無法於低電壓下操作。
在這個作品中，我們提出了陣列邊緣記憶體電路。此電路對於降低接地彈跳的主要觀念在於分散接地彈跳到其他未選擇的行之記憶胞地端。為了切換記憶胞的地線為零伏特或抬高的電壓，此電路需要兩個N型的金氧半場效應電晶體當作開關。此外，網狀線的功能是用來降低接地彈跳因為其電流可以藉由網狀線分散到其他的記憶胞地端。
透過二十八奈米互補式金氧半邏輯製程技術，建構出一容量為兩百五十六千字元之新穎記憶胞搭配雙相分離控制電路。藉由示波器以及測試機台PK2之量測，此晶片可於五百八十毫伏之操作電壓下以四百五十五百萬赫茲的頻率運行。此作品之品質因數: 記憶胞穩定性乘以寫入邊限乘以記憶胞電流為其他低操作電壓之靜態隨機存取記憶體的三十二倍。

國立清華大學 碩士論文 I
摘要 V
Abstract VII
致謝 VIII
Contents IX
List of Figure XI
Chapter 1. Introduction 1
1.1 Background 1
1.2 MOSFET Current Model at Low Voltage 5
1.3 Overview of this thesis 7
Chapter 2. Overview of Low Voltage SRAM 8
2.1 Introduction of Conventional SRAM from Chip 8
2.1.1 Types and Functions of Pins 8
2.1.2 Write Operation 10
2.1.3 Read Operation 11
2.1.4 Standby Operation 12
2.2 Introduction of Conventional SRAM from Architecture 13
2.2.1 Basic Architecture 13
2.2.2 Critical Signals 15
2.2.3 Write Operation 17
2.2.4 Read Operation 18
2.2.5 Standby Operation 19
2.3 Introduction of Conventional 6T SRAM Cell 20
2.3.1 Circuit 20
2.3.2 Write Operation 22
2.3.3 Read Operation 22
2.4 Issue for 6T SRAM Cell 23
2.4.1 Process Variation 23
2.4.2 Write Failure in Write Operation 24
2.4.3 Read Disturb in Read Operation and Half-Selected Disturb in Write Operation 25
2.5 Analysis for 6T SRAM Cell Design 26
2.5.1 Write Margin (WM) 26
2.5.2 Static Noise Margin for Read (RSNM) and Hold (HSNM) 27
Chapter 3. Design Challenges of Dual-Split Control 6T Cell 29
3.1 Background and Concept 29
3.2 Operation 31
3.3 Ground Bounce Issue 33
3.3.1 Ground Bounce Analysis in Different Operation 34
3.3.2 Ground Bounce Analysis with Different Configuration of Array 36
3.3.3 Ground Bounce Analysis with Different Corner and Voltage 37
3.4 Ground Bounce Impact 38
3.4.1 HSNM 38
3.4.2 RSNM 40
3.4.3 Summary for SNM 41
Chapter 4. Proposed Array-Edge Memory Scheme 42
4.1 Concept 42
4.2 Circuit 42
4.3 Analysis 43
Chapter 5. Low Voltage SRAM Macro Implementation 45
5.1 Structure of Proposed Scheme 45
5.1.1 Arrangement of Sub-Macros 46
5.1.2 Structure of Sub-Macros 46
5.1.3 Test Chip 47
5.2 Layout of 256kb SRAM 48
5.3 Die photo of SRAM 49
Chapter 6. Experimental Result and Conclusion 50
6.1 Chip Performance Measurement 50
6.2 Thesis Summary and Conclusion 51
Reference 55

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