摘要
3D IC是近期極為熱門的話題之一，不單是因為有可能打破存在30年之摩爾定律，也因其可縮小體積、降低功耗、提升可靠性與安全性等特性，而備受矚目。並且由於對於同樣容量之記憶體晶片，三維堆疊晶片可擁有較高之良率，進而可以節省整體晶片生產之成本。本研究提出使用三維堆疊電阻式記憶體，將利用晶片立體堆疊技術，快速提升記憶體容量。
我們使用TSV(Through Silicon Via)半導體之三維堆疊技術，設計可堆疊之三維堆疊電阻式記憶體(RRAM) 。此三維堆疊電阻式記憶體將利用三維晶片不同層的晶片可共用部分電路之特性，共用電阻式記憶體之周邊電路，以減少周邊控制電路所佔之電路面積比例，提高電阻式記憶體的記憶胞陣列所占面積比例，達到提高單位面積記憶胞陣列密度的效果，並可藉由垂直堆疊晶片讓電阻式記憶體容量倍增。
本次研究中，我們製作了一個雙層之四百萬位元非同步三維堆疊電阻式記憶體，並對於針對TSV具有的大電容特性，設計了一高速與低耗能之電流式高速傳輸電路。藉由進行垂直堆疊之三維堆疊電阻式記憶體電流式感測放大讀取電路與電流式TSV傳輸電路之整合，我們可回收電流式感測放大讀取電路所用之大電流進行TSV上之資料傳輸，並結合電阻記記憶體所需之讀取感測放大電路與電流式TSV傳輸電路，達到減少三維堆疊電阻式記憶體資料傳輸所需的時間、功耗與面積的效果。量測結果對於43pF之PCB板大電容，所需之額外傳輸時間為0.1ns，額外傳輸能量為1.8pJ.

Abstract
3D IC has become one of the most popular topics recently. It stands a chance to challenge Moore’s law and people high attention to it because it can help reduce the volume, reduce power consumption, rise reliability and security of chip. Also, for a memory with the same capacity, the memory with 3D stacked structure can have higher yield thus reduce the cost of the chip. In this research, we proposed a 3D stacked resistive random access memory (RRAM) which can enlarge the capacity of memory quickly by stacking chips.

We used TSV (Through Silicon Via) semiconductor 3D stack technology to design out 3D stacked resistive random access memory (RRAM). This 3D stacked RRAM can share the common part of circuits in different layers to reduce the area of circuits, increase the area ratio of memory array and increase the area efficiency of memory. In this way, we can build a high density RRAM. Also, we can easily double the capacity of RRAM by vertically stacking chips.

In this research, we build two- layer 4Mb non-volatile 3D stacked RRAM. Also, to deal with the large capacitance of TSV, we design a high speed and low power current TSV transmission circuit. By combining the current sense amplifier of the 3D RRAM and current mode TSV data transmission circuit, we can recycle the large current used when sensing RRAM values and used this current to transmit data on TSV. With this technique we can reduce the power consumption, area cost and access time of 3D stacked RRAM and improve overall performance. The measurement shows that the additional transmission time and energy for 47 pF PCB pad loading are 0.1ns and 1.8pJ.

Contents
摘要
Abstract ii
致謝 iii
Contents iv
List of Figures vi
List of Tables x
Chapter 1 Introduction 1
1.1 Advanced IC Technology: TSV based 3D IC 1
1.2 Emerging Non-volatile Memory: RRAM 4
1.3 Motivation and Application for 3D-RRAM 6
1.3.1 Previous 3D Memory IC Researches 6
1.3.2 TSV based 3D RRAM Memory Cube 11
1.4 Thesis Organization 12
Chapter 2 Characteristic 13
2.1 Characteristic of ITRI 3D IC Process 13
2.1.1 Introduction to ITRI 3D IC Process 13
2.1.2 RC Characteristic Analysis of ITRI 3D Process 14
2.2 Characteristic of ITRI RRAM 16
2.2.1Introduction to ITRI RRAM 16
2.2.2 RRAM operation Analysis of ITRI RRAM 17
Chapter 3 Design Challenage 19
3.1 TSV Loading Issue for Signal Transmission on TSV in 3D IC 19
3.1.1 Conventional Voltage mode TSV Transmission Scheme 20
3.1.2 Conventional Current mode TSV Transmission Scheme 22
3.2 Previous Work 23
3.2.1 Small Swing TSV Transmission Scheme 24
3.2.2 Low Swing TSV Transmission Schemes 24
Chapter 4 Proposed Circuit Scheme 26
4.1 Concepts of proposed I-Mode (Current-Mode) TSV Transmission Scheme 27
4.2 I-Mode TSV Transmission Scheme 31
4.3 Clamping Circuit 33
Chapter 5 Analysis and Comparisons 34
5.1 TSV Transmission Energy Analysis 34
5.2 TSV Transmission Time Analysis 37
5.3 Transmission Circuit Area Analysis 40
5.4 TSV Capacitance Variation Analysis 41
5.5 Summary 43
5.5.1 Analysis with TSMC 180nm Process 44
5.5.2 Analysis with TSMC 65nm Process 47
Chapter 6 Macro Implementation 52
6.1 3D RRAM Macros 52
6.2 3D TSV Transmission Scheme 55
6.3 Test Chip Design 56
Chapter 7 Experimental Results and Conclusion 58
7.1 Measurement Results 58
7.2 Future Work 60
Reference 62

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