此論文著重於設計、實作以及量測光連結系統收發端電路。第二中第三章著重於光連結系統接收電路及發射端電路並且實際應用於光元件進行光性量測。第四章提出80 Gb/s 4×4光電界面高速交換機。最後一章會做出結論並且提出未來可行的發展目標。
第二章裡，10 Gb/s 小面積無電感轉阻放大器實作於CMOS 0.18 µm製程。此電路達在0.22 pF的輸入電容負載達到頻寬7 GHz，在供應電壓1.8 V下消耗功率為9 mW。轉阻增益達到55.3 dBΩ，而核心電路面積僅為0.0065 mm2。在光性眼圖量測上此設計可以應用在10 Gb/s的光連結系統。
第三章裡，一個40 Gb/s 調變器驅動電路CMOS 40 nm製程。此電路設計應用於與University of Southampton Optoelectronics Research Center的調變器整合，量測結果此調變器驅動電路操作在12.5 Gb/s負載50 Ω的情形下可以達到1 V的輸出擺幅。在供應電壓4 V下消耗功率為377 mW，而核心電路面積僅為0.012 mm2。
第四章裡，本論文提出一個4x4 80 Gb/s STDM光電介面交換機實作於CMOS 40 nm製程。此交換機整合於光連結收發端電路，每路最高傳輸速度為20 Gb/s，光電接收端提供69.6 dBΩ 轉阻增益與21 GHz頻寬。光電發射端部分，提供8 mA 的驅動電流，整體交換機消耗功率為450 mW。靜電保護電路也被使用以防止靜電效應。

In this thesis, we focus on design, implementation, and characterization of the high speed optical transceiver for optical interconnect applications. The second and third chapters describe optical transceiver front-end, which not only design and implement of the integrated circuits but also demonstrate the optical measurements with optical devices, including photo detector (PD) and MD (Modulator Diode). The forth chapter proposes an 80 Gb/s 4×4 high speed switch combined with optical transceiver circuits with O/E interface for optical interconnect applications. Finally, the conclusion and future prospect are given.
In Chapter 2, a compact 10-Gb/s inductorless transimpedance amplifier (TIA) packaged with avalanche photo detector (PD) has been implemented and demonstrated with optical measurements. The proposed TIA fabricated in 0.18-μm CMOS achieves a 3-dB bandwidth of 7 GHz with termination of photodiode capacitance of 0.22 pF, consuming only 9 mW under the supply voltage a of 1.8 V. The transimpedance gain attains 55.3 dBΩ with a core area as small as 0.0065 mm2. The optical measurement has been demonstrated, which shows well opened eye diagram at a data rate of 10 Gb/s.
In Chapter 3, a compact 40 Gb/s inductorless Modulator driver is proposed and implemented in 40 nm CMOS for the purpose of integration with the silicon-based high speed modulator, provided by University of Southampton Optoelectronics Research Center. Measurement results demonstrate that this driver, operating at 12.5 Gb/s, can achieve a 1V swing under the termination of 50 Ω. The circuit operates at 4 V supply voltage and consumes 377mW with a core area only 0.012 mm2.
In Chapter 4, a 4×4 80 Gb/s Symmetric Time Division Multiplexing (STDM) O/E interface switch implemented in CMOS 40nm process is proposed. The maximum transmission speed is 20 Gb/s in each channel. In this switch, we combine the optical transceiver to achieve a fully-integrated high-speed switch with O/E interface for optical interconnect application. The optical receiver can generate a 69.6 dBΩ transimpedacne gain with a 21 GHz bandwidth. The transmitter provides 8 mA driving current for the laser diode. The total power consumption of the STDM switch is 450 mW at the supply voltage of 1.5 V. The extra electrostatic discharge (ESD) protection circuit is adopted in this chip to avoid transistors damage.

ABSTRACT ii
摘要 iv
CONTENTS v
LIST OF FIGURES vii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
Chapter 2 10 GB/s Optical Receiver with Indoctorless TIA and Avalanche PD 4
2.1 The Principle of TIA Design 4
2.2 Regulated Cascode Current Buffer 6
2.3 Proposed TIA in 0.18μm CMOS Technology 9
2.4 Simulation and Measurement Results 10
2.4.1 Electrical Measurement Results 11
2.4.2 Current-mode Input with Commercial PD 14
2.4.3 Current-mode Input with Si-APD 17
2.4.4 Current-mode Input with Waveguide PD 19
Chapter 3 Design of 40Gb/s Modulator Driver in 40 nm CMOS 23
3.1 The Principles of Modulator Driver Design 23
3.2 Output Stage and Impedance 25
3.3 Proposed Two-Stage Modulator Driver 28
3.3.1 Second Order Active Feedback 29
3.3.2 Cascode Output Stage 30
3.4 Simulations and Measurement Results 33
Chapter 4 80 Gb/s STDM Switch with O/E Interface 37
4.1 Introduction of STDM Switch 37
4.2 O/E Interface Switch in 40nm CMOS Technology 39
4.2.1 High-speed STDM Switch Block 40
4.2.2 Receiver Front-end 43
4.2.3 Transmitter Front-end 50
4.2.4 ESD Protection 52
4.3 Simulation and Measurement Result 53
4.3.1 Simulation Results 54
4.3.2 On wafer high speed measurement results 59
4.3.3 Switch function measurement results 60
Chapter 5 Conclusion 63
5.1 Conclusion 63
5.2 Future Work 64
References 65

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