在現今的半導體記憶體中，反及閘式快閃記憶體在大容量資料存取的應用中扮演非常重要的角色。由於元件面積是平面半導體記憶體中最小的，反及閘式快閃記憶體可以達成相當高的元件密度並且降低製造成本。為了研發更優質的產品，如何繼續增加密度、降低成本就顯得非常重要。現今最先進的反及閘式快閃記憶體已經微縮至二十奈米，平面式的反及閘式快閃記憶體微縮越來越困難，成本越來越高。既然無法縮小平面上的元件，要達成更高記憶體容量的另一個辦法就是在垂直方向堆疊更多的元件。在這樣的概念下，三維的反及閘式快閃記憶體應運而生，目前被視為下一世代大容量資料存取應用的解決方案。
不同於平面式的記憶體環境單純，在三維反及閘式快閃記憶體中，不同堆疊層具有些微的製程差異。也因此，不同堆疊層的初始臨界電壓值分布以及對於溫度產生漂移的係數也各不相同。假如我們使用相同的寫入驗證電壓去驗證所有的堆疊層，將會造成反及閘式快閃記憶體單元的耐久力下降。
我們提出一款位元線嵌位電路設計，搭配反向感測機制，即可滿足各層所需的寫入驗證電壓以及溫度補償。此款電路可以儲存多筆資料，資料內容為目標層與參考堆疊層之間的初始臨界電壓差加上目標層的溫度補償電壓。最後將這些電壓同時傳送至各自頁面緩衝器的位元線嵌位電晶體。傳統的溫度補償方式是將補償電壓加於字元線上，然而三維垂直閘架構中的字元線供應電壓給所有的堆疊層，因此無法延用。我們所提出的電路能根據個別堆疊層提供不同補償電壓能大大改善操作的精準度以及記憶體的耐久度。

In the modern semiconductor memory, NAND flash plays an important role to data storage. It can achieve high cell density and low cost with the smallest cell area in the planar semiconductor memory. To develop up-to-date product, increasing the density and decreasing the bit cost have turned into the top target. The state-of-the-art of modern NAND flash technology has reached 2X nanometer. The technology scaling has become more and more difficult and expensive. In order to conquer the restriction, the three dimensional (3D) NAND flash technology has been regarded as the solution of the next generation large data storage application in the recent year.
The three dimensional (3D) differs from the planar NAND flash memory; each layer has their unique environment. Hence the initial VTH distribution and the temperature coefficient are different from the other layers as well. The endurance of NAND flash cell will degrade if we keep applying the same program verification voltage to all layers.
To reach the goal of layer aware program verification and temperature compensation, we proposed a Bit-Line-clamp (BL-clamp) Generator that should be used with reverse sensing scheme. This proposed circuit can storage several datas that contains the initial VTH difference between target and reference layer combine with the temperature compensated voltage for target layer. And then transferring these datas to the Bit-Line-clamp transistors of each page buffer (PB) simultaneously. In the conventional way, the temperature compensated voltage is applying to the WL. However, each WL is connected to all layers in the three dimensional vertical gate (3DVG) structure. This proposed circuit offers the different compensated voltage to each layer will greatly improve the accuracy and memory endurance.

A Thesis i
指導教授推薦書 ii
口試委員審定書 iii
Abstract (Chinese) iv
Abstract(English) v
致謝 vi
Contents viii
LIST OF FIGURES xi
LIST OF TABLES xiii
Chapter 1. Introduction 1
1.1 NAND Flash Memory Application 1
1.2 Limitation of NAND Flash Memory 3
1.3 Overview of Thesis 6
Chapter 2. 3D Vertical Gate (3DVG) BE-SONOS TFT NAND Flash Memory 7
2.1 Bandgap Engineered Silicon-Oxide-Nitride- Oxide-Silicon (BE-SONOS) Memory Device 7
2.2 Array Organization 10
2.3 Read Operation 12
2.4 Program Operation 14
2.4.1 Program 14
2.4.2 Self-Boosted Program Inhibit (SBPI) Technique 15
2.4.3 Program Verification 17
2.4.4 Incremental Step Pulse Programming (ISPP) 19
2.5 Erase Operation 20
2.5.1 Hole Tunneling Erase 20
2.5.2 Self-Boosted Erase Inhibit Technique 21
2.5.3 Erase Verification 23
Chapter 3. Challenges of 3DVG NAND Flash 25
3.1 Bit Line Coupling Noise 25
3.2 Source Line Noise 29
3.3 Background Pattern Dependency (BPD) 31
3.4 Layer by Layer VTH Requirement 33
Chapter 4. Previous Sensing Scheme 35
4.1 Forward Voltage Sensing 35
4.1.1 Basic Concept 35
4.1.2 BL Interleaving Architecture 37
4.2 Forward Current Sensing 39
4.2.1 Basic Concept 39
4.2.2 Multi-Sensing Method 41
4.3 Reverse Voltage Sensing 42
4.3.1 Basic Concept 42
4.3.2 Example 43
4.4 Cache Scheme 45
4.4.1 Cache Read 45
4.4.2 Cache Program 46
4.5 Temperature Compensation 46
Chapter 5. Proposed Layer Aware Temperature Compensated BL-clamp Generator 49
5.1 Layer Aware Program Verification (LAPV) 49
5.2 Layer Aware Temperature Compensation 51
5.3 Proposed BL-clamp Generator Circuit 52
5.4 Operation 56
Chapter 6. Analysis and Comparisons 58
6.1 Components Analysis 58
6.1.1 MOS 59
6.1.2 BJT 61
6.1.3 Capacitor 63
6.1.4 Resistance 65
6.1.5 Summary 66
6.2 Comparison with Other Temperature Compensated Circuits 69
6.2.1 First Schematic 70
6.2.2 Second Schematic 71
6.2.3 Summary 72
Chapter 7. Chip Implementation 74
7.1 Test Chip Structure 74
7.2 Marco Structure 74
7.2.1 Array Organization 75
7.2.2 Periphery Circuit 76
Chapter 8. Experiment and Conclusion 78
8.1 Experiment 78
8.1.1 Test chip Photo 78
8.1.2 Function Testing 79
8.2 Conclusion and Future Work 85
Reference 87

Roberto Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory, ” in Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, April 2003.
Fujio Masuoka, M. Momodomi, Y. Iwata and R. Shirota, “New ultra high density EPROM and flash EEPROM with NAND structure cell,” in Int. Electron Devices Meeting (IEDM), vol. 33, pp. 552-555, 1987.
M. Bauer et al., “A multilevel-cell 32 Mb flash memory,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 132-133, Feb. 1995.
H.Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 14-15, June 2007.
Marvin White, D. Adams, and J. Bu “On the go with SONOS,” in IEEE Circuits and Designs, vol. 16, pp. 22-31, July 2000.
Jaehoon Jang et al., “Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 192-193, June 2009.
Ryota Katsumata et al., “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 136-137, June 2009.
Jiyoung Kim et al., “Vertical-Stacked-Array-Transistor (VSAT) for ultra- high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive),” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 186-187, June 2009.
Hang-Ting Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, pp. 547-550, Dec. 2005.
Hang-Ting Lue et al., “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 131-132, June 2010.
Rich Liu, H. Lue, K.C. Chen, and C. Lu, “Reliability of Barrier Engineered Charge Trapping Devices for Sub-30nm NAND Flash,” in Int. Electron Devices Meeting (IEDM), pp. 1-4, Dec. 2009.
Hang-Ting Lue, Rich Liu, “A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method-Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices,” in IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2218-2228, Aug. 2008.
Chun-Hsiung Hung et al., “3D Stackable Vertical-Gate BE-SONOS NAND Flash with Layer-Aware Program-and-Read Schemes and Wave-Propagation Fail-Bit-Detection against Cross-Layer Process Variations,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. C20-C21, June 2013.
Kang-Deog Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 128-129, Feb. 1995.
Tomoharu Tanaka et al., “A quick intelligent program architecture for 3 V only NAND-EEPROMS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 20-21, June 1992.
G. J. Hemink et al., “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 129-130, June 1995.
Rino Micheloni, Luca Crippa, and Alessia Marelli, “Inside NAND Flash Memories,” ISBN 978-90-481-9430-8.
Koichi Fukuda et al., “A 151mm2 64Gb MLC NAND Flash Memory in 24nm CMOS Technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 198-199, Feb. 2011.
Ken Takeuchi et al., “A double-level-vth select gate array architecture for multi-level NAND flash memories,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 69-70, June 1995.
Tommaso Vali et al., U.S. Patent No. 7936606 – Compensation of back pattern effect in a memory device, Assignee: Micro Technology, Inc.
Young-Bog Park et al., “Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a Flash EEPROM,” in IEEE Transactions on Electron Devices, vol. 45, pp. 1361-1368, June 1998.
Kenichi Imamiya et al., “A 130 mm2 256 Mb NAND flash with hallow trench isolation technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 112-113, Feb. 1999.
Hiroshi Nakamura et al., “A novel sense amplifier for flexible voltage operation NAND flash memories,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 71-72, June 1995.
Tomoharu Tanaka et al., “A quick intelligent page programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory,” in IEEE J. Solid-State Circuits, vol. 29, pp. 1366-1373, Nov. 1994.
Raul Cernea et al., “A 34 MB/s-program-throughput 16 Gb MLC NAND with all bitline architecture in 56 nm,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, pp. 420-624, Feb. 2008.
Raul-Adrian Cernea et al., U.S. Patent No. 7443757 – Non-volatile memory and method with reduced bitline crosstalk errors, Assignee: SanDisk Corporation.
Ken Takeuchi et al., “A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories,” in IEEE Symposium on VLSI Technology Dig. Of Tech. Papers, pp. 234-235, June 1998.
June Lee et al., “A 1.8V 1Gb NAND Flash Memory with 0.12um STI Process Technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Paper, vol. 2, pp. 80-410, Feb. 2002.
Kenichi Imamiya et al., “A 125-mm2 1-Gb NAND Flash Memory With 10-MByte/s Program Speed,” in IEEE J. Solid-State Circuits, pp. 1493-1501, Nov. 2002.
Luca Crippa et al., U.S. Patent No.7474577 – Circuit and method for retrieving data stored in semiconductor memory cells, Assignee: STMicroelectronics/Hynix Semiconductor.
Toru Tanzawa et al., U.S. Patent No.5864504 – Nonvolatile semiconductor memory with temperature compensation for read-verify referencing scheme, Assignee: Kabushiki Kaisha Toshiba.
Tae-Hee Cho et al., U.S. Patent No.6870766 – Multi-level Flash memory with temperature compensation, Assignee: Samsung Electronics Co., Ltd.
Takayuki Kawahara et al., “Bit-Line Clamped Sensing Multiplex and Accurate High Voltage Generator for Quarter-Micron Flash Memories,” in IEEE J. Solid-State Circuits, pp. 1590-1600, Nov. 1996.