本篇論文中，我們使用厚磊晶之氮化鎵試片製作準垂直型PiN二極體，並解決製程上遇到之問題。我們原設計比較不同表面鈍化層對元件的影響，在正向量測方面電流密度在10V可達1243A/cm2，導通電壓為4.0V，Ron,sp 為3.76 m-cm2。在反向特性方面我們對漏電流成分進行分析，鈍化層在低壓時可抑止元件漏電流，且含鈍化層元件之崩潰電壓可達1000V。我們也量測升溫特性，成功以Su-8保護層方式解決高溫下的崩潰量測問題，在200℃下崩潰電壓達到700V。
為了解決P型歐姆接觸的問題，我們更動製程順序成P型歐姆接觸先行製作，而元件特性皆有所提升。順向特性方面與原製程相比，電流密度在10V達到1768A/cm2，較原製程提升了40，導通電壓降為3.5V 、Ron,sp 為2.67 m-cm2 降低了25，崩潰電壓也有900V，達現有文獻之水準。我們分析並推測幾種可能造成歐姆接觸退化之原因，但詳細的製程影響仍尚待釐清，以現有結果我們認為P型歐姆接觸先做的製程能達成相對良好的元件，而詳細的製程影響需要未來進一步研究。

In this thesis, we fabricated a quasi-vertical PiN diode by thick-epi GaN on a sapphire substrate. Different passivation process was investigated to see their influences on leakage characteristics. In the first fabrication attempt, the best data of forward current is 1243A/cm2 at 10V with a turn on voltage of 4.0V, and specific turn on resistance was 3.76 m-cm2. The passivation layer could suppress reverse leakage current at lower bias, and improved breakdown voltage over 1000V. To measured high temperature reverse bias characterization, we developed the Su-8 coating method and measured 700V breakdown at 200℃ successfully.
In the second attempt, with an improved fabrication sequence to put p-contact first, the forward current density at 10V was improved to 1768A/cm2 at 10 V , about 40 enhancement than the first run, and the turn on voltage was reduced to 3.5V, specific turn on resistance was reduced to 2.67 m-cm2. We analyzed the differences of this two fabrication sequences and speculated the reason was the P type ohmic contact degradation. We concluded that the p-contact first process was better design, but still have to verify by more detail experiments.

目錄
中文摘要 II
Abstract III
目錄 IV
圖目錄 VII
表目錄 XI
第1章 序論 1
1.1 前言 1
1.2 研究動機與文獻回顧 3
1.3 研究方向簡介與論文架構 9
1.3.1研究方向簡介 9
1.3.2論文架構 9
第2章 元件介紹與實驗設計 10
2.1 氮化鎵材料介紹及基板選擇 10
2.2 PiN二極體原理 12
2.2.1 順向導通特性 12
2.2.2 逆偏耐壓特性 14
2.3 高台結構(mesa structure)之深蝕刻 16
2.4 P型歐姆接觸製作與特性介紹 17
2.4.1 P型半導體之摻雜與活化 18
2.4.2 P型歐姆接觸之金屬選擇 19
2.4.3 表面處理之影響 20
2.4.4 P型金屬退火燒結 21
2.5 元件設計與模擬 24
2.5.1 實驗之GaN磊晶介紹 24
2.5.2 元件設計與模擬 27
2.5.2 元件Layout設計 30
2.5.3 實驗目標 31
第3章 光罩設計與元件製程 32
3.1 準垂直型PIN元件設計流程 32
3.2 對準記號蝕刻(Mask1) 33
3.3 蝕刻遮罩與深蝕刻(Mask2) 34
3.3.1 蝕刻遮罩 34
3.3.2 深蝕刻 35
3.4 活化與表面鈍化 37
3.5 N型歐姆接觸(Mask3) 38
3.6 P型歐姆接觸(Mask4) 38
3.7 襯墊金屬(Mask5) 39
第4章 量測結果分析 42
4.1 正向電性分析 42
4.1.1 N型歐姆接觸分析 42
4.1.2 P型歐姆接觸分析 44
4.1.3 元件順向偏壓量測 46
4.1.4 元件不同尺寸量測 48
4.2 反向電性分析 50
4.3 崩潰特性分析 53
4.3.1 崩潰量測 53
4.3.2 場平板對崩潰電壓影響分析 57
4.4 升溫特性分析 58
4.4.1 升溫順向特性 58
4.4.2升溫崩潰特性分析 61
4.5 製程改進 66
4.5.1 P ohmic first元件量測 67
4.5.2 原因分析與製程檢討 71
第5章 結論與未來工作 73
第6章 參考文獻 74

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