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作者(中文):王志銘
作者(外文):Wang, Jhih-Ming
論文名稱(中文):28奈米互補式金氧半金屬閘極製程高壓金氧半場效電晶體
論文名稱(外文):Floating Field Plate HV-MOSFET by 28nm High-k Metal Gate Process
指導教授(中文):金雅琴
口試委員(中文):林崇榮
蔡銘進
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:100063510
出版年(民國):102
畢業學年度:101
語文別:中文
論文頁數:66
中文關鍵詞:功率元件
外文關鍵詞:28nm high-k metal gatefield platefield limiting ring
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近年來,隨著能源議題的重要性增加,電力電子和功率元件的發展亦成為關鍵之一。如何獲得良好的耐壓能力與導通阻值的權衡和降低製作成本一直是功率元件的研究重點,儘管許多研究發表只需少數光罩即可完成,但仍為特殊製程,需藉由打線接合(Wire bonding)技術將功率元件和主要電路部分連接,在成本降低以應用彈性上仍然受限。此外,一般金氧半場效電晶體的崩潰電壓,容易受到表面峰值電場影響,也是會造成金氧半場效電晶體的閘極介電層可靠度降低。本論文提出一個可整合於28奈米互補式金氧半金屬閘極製程的功率元件,稱為浮空場板金氧半場效電晶體 (Floating Field Plate MOSFETs)。薄閘極介電層下,藉由浮空的金屬閘極被使用延伸在汲極接面邊緣的擁集電場,以提高耐壓。透過TCAD(Tsuprem4 and Medici)模擬器,分析其浮空場板設計對於電位與表面電場分布的影響;從量測結果顯示浮空場板金氧半電晶體可以有效的改善閘極引致崩潰(Gated breakdown),使其電壓接近接面崩潰。因此元件不需漂移區(Drift region)光罩且不需額外的打線接合技術,故可降低製作成本及增加高壓電路設計之彈性應範圍。
In recent years, the improvement of power electronics and power devices is one of key forces for energy efficient appliances in modern day lives. Continuous cost down and the tradeoff between breakdown voltage and on-resistance have always been major concerns in designing power devices. Most of the power devices in IC require some or substantial changes from generic CMOS process. However, these special processes and/or discrete power devices connected through wire bonding prevent the power circuits to be cost down further.On the other hand, scaled COMS technology creates high surface electric field, which seriously limit its operation voltage. It will be very hard to design HV circuits in advance CMOS technologies due to lack at HV devices. This work presents floating field plate (FFP) design for 28nm high-k metal gate MOS transistors. Floating metal gates are employed to extend the corner electric field at edge of drain junction under the thin core gate dielectric layer. The design of floating field plate on potential profiles and surface electric field distributions are studied by simulation data. Measurement results demonstrated that the floating field plates can effectively raise the gated breakdown voltage to the junction limit without process modifications. This fully logic compatible device does not need the additional masks of and/or wire bonding process for connection, hence, can be extended to various applications such as embedded memories.
摘要 ................... i
Abstract .............. ii
致謝 ...................iii
內文目錄 ................iv
附圖目錄 ................vi
表格目錄 ................viii
第一章 序論 .............1
1.1 研究動機 ............1
1.2 章節介紹 .................. 2
第二章 耐壓元件操作原理與發展回顧 ...3
2.1 耐壓元件操作原理............. 3
2.1.1 MOSFET 功率元件之導通特性與耐壓機制............. 3
2.1.2 MOSFET 功率元件之崩潰機制 ................. 4
2.1.3 邊際效應 ................ 6
2.2 場限環及場板其原理與基本架構 ..................... 7
2.3 小結 ................................ 9
第三章 元件設計與模擬 ............................... 21
3.1 浮空場板金氧半場效電晶體元件設計概念 ................. 21
3.2 浮空場板金氧半場效電晶體元件特性模擬 ............... 22
3.2.1 崩潰模擬特性分析 ................................................ 23
3.2.2 導通模擬特性分析 ................................................. 23
3.3 浮空場板金氧半場效電晶體特性探討..................... 24
3.4 小結 .................................. 26
第四章 元件製備與量測特性分析 ......................... 44
4.1 元件製程流程 ...................................... 44
4.2 浮空場板金氧半場效電晶體特性量測與探討 .......... 45
4.2.1 崩潰特性量測結果 ................................. 45
4.2.2 導通特性量測結果 ............................... 46
4.3 元件可靠度分析 ........... 47
4.4 小結 .............................. 47
第五章 結論 ............................... 63
參考文獻 ................................ 64
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