三維積體電路相對於二維積體電路而言有許多優點，如更短的全域線
長和較佳效能。模組元件與矽晶穿孔(Through-Silicon Via)的位置
在決定線長時扮演了重要的角色。我們使用疊代法在白空間重新分配
來改善全域線長。在每個改善步驟中我們建立並更新約束圖，白空間
重新分配被制定成兩組線性規劃(Linear Programming)並被最新發
展的解算器所解決。實驗數據顯示在所有的測試裡該演算法可以達到
最高7.3%的線長縮短並只花費少量時間。

Three dimensional integrated circuit (3-D IC) technique has various of benefits compared to traditional two dimensional IC (2D-IC) such as shorter global interconnect and higher performance. Positions of module blocks and Through-Silicon-Vias(TSV) plays an important role in total wirelength. To reduce the total wirelength, we use an iterative white space
redistribution algorithm to improve the global interconnect. Constraint graph is constructed and updated during each refinement step, the whitespace redistribution is formulated as two linear programs and solved by an state-of-the-art optimizer. The experimental result shows the algorithm can achieve at most 7.3% wirelength reduction over all testcases and the runtime is very fast.

Contents
Acknowledgement i
Abstract ii
1 Introduction 1
1.1 Introduction . . . 1
1.2 Previous work . . . 2
1.3 Organization . . . 3
2 Preliminaries and Problem Formulation 5
2.1 Block Level Floorplan with TSV Co-Placement. . . 5
2.2 TSV Reassignment . . . 7
2.3 Wirelength Estimation . . . 9
2.4 Whitespace redistribution for wirelength minimization on 3D-IC . . . 10
3 Algorithm 11
3.1 Construction of Constraint graph . . . 12
3.2 LP Based Whitespace Redistribution on 3D-IC. . . 14
4 Experiment 18
4.1 Environment . . . 18
4.2 White space redistribution on 3D-IC floorplan . . . 19
5 Conclusion 25
Reference 26

[1] X. He, S. Dong, Y. Ma , X. Hong, “Simultaneous buer and interlayer via planning
for 3D floorplanning ” in Proc. of International Symposium on Quality of Electronic
Design 2009
[2] M.-C Tsai, T.-C.Wang, T.T. Hwang, “Through-Silicon Via Planning in 3-D Floorplanning
,” in IEEE Trans. Very Large Scale Integration (VLSI) Systems, Volume: 19 ,
Issue: 8 , pp. 1448 - 1457, Aug. 2011.
[3] J. Knechtel , I.L. Markov, J. Lienig, “Assembling 2-D Blocks Into 3-D Chips” in Proc.
of the international symposium on Physical design , pp. 81-88, 2011.
[4] J. Knechtel, I.L. Markov, J. Lienig, M. Thiele, “Multiobjective optimization of
deadspace, a critical resource for 3D-IC integration ” in Proc. of IEEE/ACM International
Conference on Computer-Aided Design, pp. 705-712, 2012.
[5] D.-H. Kim, R.-O. Topaloglu, S.-K. Lim, “Block-level 3D IC design with throughsilicon-
via planning” in Proc. of Asia and South Pacific Design Automation Conference
pp.335-340, 2012.
[6] C.-R. Li,W.-K. Mak, and T.-C.Wang, “Fast Fixed-Outline 3-D IC FloorplanningWith
TSV Co-Placement,” in IEEE Trans. Very Large Scale Integration (VLSI) Systems,
Volume:21 , Issue: 3, pp.523-532, Apr. 2012.
[7] T.-C. Chen, Y.-W. Chang, and C.-C. Lin, “IMF: Interconnect-driven multilevel floorplanning
for large-scale building-module designs,” in Proc. of IEEE/ACMInternational
Conference on Computer-Aided Design, pp. 159-164, 2005.
[8] X. Tang, R. Tian and M.D.F. Wong, “Minimizing wire length in floorplanning”, in
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Volume:25 ,
Issue: 9, pp.1744-1753, 2006.
[9] J. Z. Yan and C. Chu, “DeFer: Deferred Decision Making Enabled Fixed-Outline
Floorplanner”, in Proc. of the Design Automation Conference, pages 161-166, 2008.
[10] GSRC floorplan benchmarks.
http://vlsicad.eecs.umich.edu/BK/GSRCbench/.
[11] hMetis: hypergraph partitioner.
http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview
[12] CS2: min-cost flow solver.
http://www.igsystems.com/cs2/index.html
[13] Gurobi Optimizer
http://www.gurobi.com/