大部分傳統的可程式化邏輯陣列(FPGA)使用查著表(LUT)作為基本的邏輯單位。而適性邏輯模組(ALM)是一個被Altera所採用的一種新的硬體架構來作為可程式化邏輯陣列的基本邏輯單位。適性邏輯模組可以實作單一的布林函數或是兩個比較小的查著表。對於採用適性邏輯模組的可程式化邏輯陣列之設計流程中，做完技術映射所產生的查著表必須被放進適性邏輯模組之後才能做複合邏輯單位(CLB)的叢集。這些查著表要如何被放進適性邏輯模組以及適性邏輯模組要如何分配到複合邏輯單位裡會對之後放置與繞線的品質產生巨大的影響。在這篇論文中，我們提出了一個線長導向的叢集演算法來合併查著表及分裝適性邏輯模組以確保做完叢集之後的結果不會對最後線長產生不好的影響。實驗結果顯示，針對適性邏輯模組式的可程式化邏輯陣列，相對於AAPack[8]，ALMpack的最小繞線軌道減少了14.54%而且有17.97%的線長改進。對於傳統查著表基礎的可程式化邏輯陣列，比起T-VPack[9]，最小繞線軌道ALMpack也能減少16.59%以及得到17.57%的線長改進。

Most traditional field programmable gate arrays (FPGAs) use look-up table (LUT) as the
basic logic block. Adaptive logic module (ALM) is a novel structure of logic block adopted
by Altera’s Stratix II [13] and later generations of Stratix family. An ALM can serve as one
6-input lookup table (LUT) or two smaller lookup tables under certain constraints. In a
typical design flow, a netlist of LUTs formed after technology mapping has to be merged
into ALMs and then packed into coarse-grained logic blocks (CLBs) before placement and
routing. How the LUTs are merged and the ALMs are packed has a significant impact on
the quality of the placement. We propose a novel wirelength-driven algorithm to merge the
LUTs and pack the ALMs to ensure that it will not adversely aect the final wirelength. Experimental
results show that substituting AAPack [8] by our algorithm yields about 14.54%
reduction in number of tracks and 17.97% wirelength improvement for ALM-based FPGA.
Applying our algorithm to traditional FPGA, the minimum number of tracks and wirelength
are reduced by 16.59% and 17.57%, respectively, compared to T-VPack [9].

Acknowledgement i
Abstract ii
1 Introduction 1
2 Preliminaries 4
2.1 The Idea of Safe Clustering 4
2.2 Problem formulation 7
3 Algorithm 8
3.1 Merge LUTs into ALMs 8
3.2 CLB clustering 12
4 Experiment 16
5 Conclusion 25
Reference 26

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http://lemon.cs.elte.hu/trac/lemon