由於封裝對晶片整體的熱傳導有非常大的影響，在做晶片熱分析時應一併考慮封裝和散熱扇的問題。在本論文第一個研究中，我們將說明獲取一個準確的模擬用封裝模型的困難，並探討不同封裝種類對全晶片之熱響應。為了使晶片設計者能夠易於在各種封裝環境下進行熱模擬，我們提出使用「封裝轉換矩陣(Package-Transfer Matrix, PT-matrix)」，將同一晶片在一封裝下之溫度分布轉換為另一封裝下之溫度分布。為評估及驗證封裝轉換矩陣的準確性，我們採用兩個我們設計之 PBGA 封裝的測試晶片及紅外線放射儀(Infrared Radiation, IR)。實驗結果顯示封裝轉換矩陣能準確地將使用軟體 HotSpot 預設之 CBGA 封裝模擬的溫度分布轉換為任一種封裝型態下的溫度分布。此外，採用矽穿孔(Through Silicon Via, TSV)技術的三維或 2.5 維堆疊晶片系統中，熱與其造成的機械問題較傳統二維晶片嚴重許多。先前研究提出許多矽穿孔擺放方法以減輕操作時的熱點問題、或減少繞線長度。但除上述問題外，我們證明矽穿孔的擺放方式亦會影響晶片破裂發生的機率。本論文第二個研究即根據 Gur Game 提出一種新穎的矽穿孔擺放方法，同時考量晶片製程中可靠度、繞線長度及晶片操作時熱點的影響。

Since packages affect the amount of heat transfer, it is important to include package and heat sink in thermal analysis. In the first work of this thesis, we study the full-chip thermal response with different packages. We first discuss the difficulties of obtaining accurate package models for simulation. To facilitate a designer to perform thermal simulation with different packages, we propose to use a matrix called the package-transfer matrix (PT-matrix), which can transform a temperature profile of one package to another temperature profile of the desired package. To estimate and verify a PT-matrix, we propose an efficient method which uses infrared radiation images from two carefully design test chips with PBGA packages. Furthermore, thermal and thermal-induced mechanical problems in 3D or 2.5D stacking-die technologies using through-silicon-via (TSV) technology are known to be more severe than those in 2D circuits. Many researchers have proposed efficient design for TSV reliability to alleviate the hot spot problem and to reduce the wire-length. However, in addition to the thermal and wire-length issues, we show that TSV reliability can be enhanced by reducing the die fracture. In the second work of the thesis, we propose a novel design methodology based on Gur Game for stacking-IC reliability simultaneously considering die fracture, temperature, and wire-length constraints.

List of Contents VI
List of Figures VII
List of Tables VIII
Chapter 1 INTRODUCTION 1
Chapter 2 PRELIMINARIES 7
2.1 Package-Induced Thermal Profile and Thermal Modeling 7
2.2 Fracture and Fracture Mechanics Modeling 11
Chapter 3 GEOMETRIC-AWARE PACKAGE-CHIP THERMAL ANALYSIS 16
3.1 Problem Description 16
3.2 Efficient Method of Approximating a PT-Matrix 18
3.2.1 The Special Characteristic of a PT-matrix 18
3.2.2 The Approximation of a PT-matrix 22
3.2.3 The Overall PT-matrix Application and Verification 26
Chapter 4 RELIABILITY-AWARE 3DIC DESIGN 28
4.1 Introduction of Gur Game 29
4.2 Thermal and Fracture Aware TSV Placement 31
4.3 The Overall TSV Placement Algorithm 33
Chapter 5 EXPERIMENTAL RESULTS 36
5.1 Geometric-Aware Package-Chip Thermal Analysis 36
5.1.1 Thermal Test Chips and Infrared Radiation Camera 36
5.1.2 PT-Matrix Establishment and Package-Chip Simulation 40
5.2 Thermal ad Fracture Aware TSV Placement 43
Chapter 6 CONCLUSIONS 52
REFERENCES 53

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