現在的系統晶片設計到產出的流程中，後段偵錯所花的時間已達到整個設計的百分之五十以上。晶片產出的流程中從前段到後段，對產品偵錯的成本是一非線性的成長速度，也因此我們需要去對偵錯來做設計。在現今多核心平台上，許多的處理器以及相關的IP都會去各自先做驗證，然而，由於整個系統複雜度的增加以及成本的考量，我們將研究重點放在對於處理器與處理器之間的傳輸來做更有效率地偵錯。

在此論文中，我們提出一個偵錯的流程並設計交易層級內嵌式追蹤器架構。根據負責處理器與處理器之間負責傳輸的硬體元件以及晶片網路來設計追蹤器，藉由觸發所要追蹤的傳輸事件知道處理器上的傳輸，並利用這些資訊來偵錯。
藉由提出的偵錯流程，我們預期在電子系統交易層級、暫存器轉移層級、FPGA都能夠實作。藉由追蹤器的幫助之下，我們可以簡單的評估軟體在資料傳輸上的效率。而在我們實作的過程也實際的解決數個原先硬體設計錯誤所產生的問題。最後，我們為了證明此偵錯流程可以適合不同層級的實作來減低開發時間之可行性，我們實作了電子系統交易層級以及暫存器轉移層級。

在實際的例子中，我們得出我們的資料壓縮率為99.77%。相對於前一版(C.-L.’s work)減低了38.8%~98.8%的資料量，使得追蹤資料可以更為及時的在合理的追蹤腳位數目下傳送出來。並提供藉由追蹤資料所估計的資料吞吐量。除此之外，在.13μm的製程，我們的追蹤器占的面積是40K gates，占整個平台的面積約為1.49%。

1 Introduction 1
1.1 Introduction of SoC Trace and Debug . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Challenge of Trace and Debug on Many-Core SoC . . . . . . . . . . . . 3
1.3 Motivation and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Previous Work 8
2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Open Core Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 OpenRISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Overview of Existent Many Core Platform . . . . . . . . . . . . . . . . . . . 11
2.2.1 Processing Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Communication Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Network on Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Software Communication Library . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Overview of Previous OCP Bus Tracer . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 OCP Bus Tracer on Many-Core Platform . . . . . . . . . . . . . . . . 18
2.5 Existent Method for Trace and Debug . . . . . . . . . . . . . . . . . . . . . 19
3 Component of Communication Tracer and Implementation 22
3.1 Overview of Communication Tracer . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Time Event Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Introduction to Time Event Trace . . . . . . . . . . . . . . . . . . . 27
3.3 API Event Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.1 API Event Trace Content . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.2 Detail of Tracing API Event . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.3 API Event Generator FSM . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4 NoC Transaction Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.1 Trace Data Reduce - Trace NoC when Direction Turned . . . . . . . 38
3.5 Trace Data Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5.1 Local Counter and Compression Unit . . . . . . . . . . . . . . . . . . 39
3.5.2 Trace Data Reduce - Nack Counter . . . . . . . . . . . . . . . . . . . 42
3.5.3 Packeting Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.4 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Proposed Trace and Debug Flow and Case Study 49
4.1 The Flow of Debugging on the many-core platform . . . . . . . . . . . . . . 49
4.2 Demonstrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.1 Simulation Model for Application-Level Debugging . . . . . . . . . . 52
4.2.2 Case Study 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.3 Case Study 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.4 Case Study 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.5 Case Study 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5 Experiment Result and Analysis 64
5.1 Trace Data Size Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.1 NoC Packet Reduce Experiment . . . . . . . . . . . . . . . . . . . . . 64
5.1.2 API Packet Reduce Experiment . . . . . . . . . . . . . . . . . . . . . 66
5.1.3 Comparison with Dierent Level Tracing . . . . . . . . . . . . . . . . 71
5.2 Communication Time Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.1 Communication Time and Computation Time . . . . . . . . . . . . . 73
5.2.2 Analyze the Two Version Oddeven Sort in Communication Time . . 73
5.3 Synthesis Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6 Conclusion and Future Work 78
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendices 80
Appendix .A ESL Global Addressing Space on Many-Core Platform . . . . . . 81
Appendix .B Communication Unit Addressing Space Used in A Processing Element 82

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