為了提高三維晶片的良率，矽穿通道的容錯技術是很重要的。在本文中，將會介紹一個使用測試矽穿通道來修復矽穿通道的架構。由於這個架構，冗餘矽穿通道的數量及所占的面積都將會減少。此外，使用的三維晶片掃描鏈最佳化演算法考慮了功能矽穿通道以及測試矽穿通道的位置。因此，測試矽穿通道及冗餘矽穿通道的總數將會有效地降低。在實驗中，利用本文中提出的方法可以降低40%矽穿通道的數量，並且只有多了3%的繞線成本。

In order to increase the yield of 3-D IC, fault-tolerance technique to recover failed TSV is essential. In this paper, an architecture of TSV recovery by using scan-chain test TSV is proposed. With the architecture, only a small amount of redundant TSVs is required to be inserted. Extra TSV area that occurs by our method is much less than that of other methods. Moreover, a 3-D IC scan-chain optimization algorithm is proposed taking into consideration the locations of functional TSVs as well as test TSVs, so that the number of total TSVs including test TSV and extra redundant TSV of a 3-D IC design is effectively reduced.

Contents
1 Introduction.................................1
2 Preliminary and Problem Denition.............4
2.1 Architecture for TSV Recovery..............4
2.2 Fault Model................................5
2.3 3-D IC Scan Chain Structure................5
2.4 TSV Redundancy using Test TSV and MUX Configuration...8
3 Algorithm...................................10
3.1 Overview of Our Proposed Method...........10
3.2 Initial Scan Chaining.....................11
3.2.1 Wire Length.............................12
3.2.2 Congestion Cost.........................13
3.2.3 Repairing Cost..........................13
3.3 Functional TSV Assignment.................14
3.4 Redundant TSV Insertion...................19
3.5 Re-chaining...............................20
4 Experimental Results........................21
5 Conclusions.................................26

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