傳統上，我們希望一個電路能夠完全執行正確，沒有任何錯誤發生。然而，對於一些可容忍錯誤的應用，如：影像處理，100%的正確性也許不是必需的。一項有趣的研究指出，如果可以不追求100%的正確性，則可以在能量消耗上獲得大量的好處，此種電路稱為機率性布林邏輯電路。近年來，機率性布林邏輯電路已被提出，在開發最佳化的演算法之前，需要一個有效的方法來分析此種電路的正確性。本文中提出了一個統計的方法，可以快速且準確的分析出機率性布林邏輯函數的正確性。實驗結果顯示我們提出的方法平均上比運算完全正確答案的方法快了122倍，而且有很小的誤差。我們也提出了一個最佳化的方法來使用機率性布林邏輯電路，在使用固定數量的機率性邏輯閘時，我們的方法可以確保機率性邏輯電路保持較高的正確性。例如：C1355這的電路，當機率性邏輯閘的數量佔總邏輯閘數量的60%以下時，我們最佳化的方法可以讓電路維持相當高的正確性。

Traditionally, we expect that the designs can be performed without errors. However, for error-resilience applications, e.g., image processing, 100% correctness is not a must. An interesting study reveals that if we do not pursue 100% correctness for the operations, the energy consumption would be significantly reduced. Recently, Probabilistic Boolean Circuits (PBCs) have been proposed. However, prior to developing the algorithms for PBC optimization, having an efficient method for correctness analysis is necessary. In this paper, we propose a statistical approach that efficiently and accurately evaluates the correctness of PBCs. The experimental results show that the proposed approach performs about 122 times faster than the golden result method on average with little correctness difference. We also propose an optimization strategy that assigns probabilistic gates with little correctness suffering, e.g., when the percentage of probabilistic gates in C1355 is <60%. Thus, the proposed approaches are very promising.

中文摘要
Abstract
誌謝辭
Contents
List of Tables
List of Figures
1 Introduction
2 Preliminaries
2.1 Probabilistic CMOS
2.2 Probabilistic Boolean Logic
2.3 Definition of Correctness
3 Methodologies
3.1 Naive Approaches
3.1.1 Exact Method
3.1.2 Formula-based Method
3.2 The Proposed Approach
3.2.1 Random Pattern Generation
3.2.2 Sampling Rule
3.2.3 Scoring
3.2.4 Error Estimation
3.2.5 Overall Flow
3.3 Optimization Strategy for the Correctness
4 Experimental results
5 Conclusion and Future Work

[1] R. S. Asamwar et al., “Successive image interpolation using lifting scheme approach,” Journal of Computer Science, vol. 6, pp. 969-978, 2010.
[2] K. Binder et al., “Monte Carlo methods in statistical physics,” Springer-Verl, 1988. [3] C. M. Bishop, “Pattern Recognition and Machine Learning”, Springer, 2006.
[4] L. N. B. Chakrapani et al., “A probabilistic Boolean logic and its meaning,”
Technical Report of Department of CS, Rice University, 2008.
[5] L. N. B. Chakrapani, “Probabilistic Boolean logic, arithmetic and architectures,”
Ph.D Dissertation, Georgia Institute of Technology, 2008,
[6] L. N. B. Chakrapani et al., “Probabilistic design: A survey of probabilistic CMOS technology and future directions for terascale IC design,” in VLSI-SoC: Research Trends in VLSI and Systems on Chip,, vol. 249, pp. 101-118, Springer Boston,
2008.
[7] S. C. Chang et al., “TAIR: testability analysis by implication reasoning,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 152-160, 2000.
[8] S. Cheemalavagu et al., “A probabilistic CMOS switch and its realization by exploiting noise,” in Proc. VLSI-SoC, pp. 452-457, 2005.
[9] M. R. Choudhury, et al., “Reliability analysis of logic circuits”, IEEE trans. on
Computer-Aided Design, vol. 28, no. 3, pp. 392-405, 2009.
[10] C.-C. Chiou et al., “A Statistic-based approach to testability analysis,” in Proc.
Int. Symposium on Quality Electronic Design, pp.267-270, 2008.
[11] L. H. Goldstein, “Controllability/observability analysis of digital circuits,” IEEE Trans. Circuits Systems, vol. CAS-26, pp. 685-693, 1979.
[12] V. Gupta et al., “IMPACT: IMPrecise adders for low-power approximate comput- ing,” in Proc. Int. Symposium on Low Power Electronics and Design, pp. 409-414,
2011.
[13] ITRS, “International technology roadmap for semiconductors,” 2007.
[14] M. Keating et al., “Low power methodology manual: for system-on-chip design,”
Springer, 2007.
[15] S. W. Keckler et al., “Multicore processors and systems,” Springer, 2009.
[16] Smita Krishnaswamy et al., “Probabilistic transfer matrices in symbolic reliability analysis of logic circuits”, ACM Trans. Design Automation of Electronic Systems, vol. 13, no. 1, article 8, 2008.
[17] R. V. Hogg et al., “Introduction to mathematical statistics,”, Pearson, 2012, [18] T. M. Mitchell, “Machine Learning,” McGraw-Hill Science, 1997.
[19] I. R. Miller et al., “Probability and statistics for engineers,” Englewood Cliffs, NJ: Prentice Hall, 1990.
[20] C. Piguet, “Low-power CMOS circuits: technology, logic design and CAD tools,”
CRC Press, 2006.
[21] D. Shin et al., “A new circuit simplification method for error tolerant applications,”
in Proc. Design, Automation and Test in Europe, pp.1-6, 2011.
[22] A. J. Strecok, “On the calculation of the inverse of the error function, mathematics of computation,” Mathematics of Computation, vol. 22, no. 101, pp. 144-158,
1968.
[23] P.-N. Tan et al., “Introduction to Data Mining”, Addison-Wesley, 2005.
[24] S. Venkataramani et al., “SALSA: systematic logic synthesis of approximate circuits,” in Proc. Design Automation Conference, pp. 796-801, 2012.
[25] S.-C. Wu et al., “Novel probabilistic combinational equivalence checking”, IEEE Trans. Very Large Scale Integration Systems, pp.365-375, 2008.
[26] http://iwls.org/iwls2005/benchmarks.html
[27] http://www.intel.com/go/terascale/