由於對硬體設計進行徹底的功能性驗證在實際上並不可行，許多覆蓋率的指標已經廣泛的被使用在功能驗證上，藉此避免多餘的重複驗證，以及當作一個測試資料的完整性指標。然而，在現今的硬體加速模擬環境中，覆蓋率的測量可能會橫跨軟體模擬器以及硬體加速器，所以傳統上只能應用在軟體模擬器上的覆蓋率測量方法，或是只能應用在硬體加速器上的覆蓋率監測方法，皆無法繼續沿用。在此篇論文中，為了在硬體加速模擬環境測量覆蓋率，我們提出了使用覆蓋率斷言去偵測橫跨軟體模擬器以及硬體加速器的覆蓋率事件，此外在硬體加速模擬環境測量覆蓋率會造成額外的硬體和效率負擔，我們也提出了一個斷言運作圖，以及運作在斷言運作圖上的演算法，藉此最佳化覆蓋率斷言所造成的負擔。我們展示了多種覆蓋率指標可以成功的運作在硬體加速模擬環境中，實驗結果也顯示了我們可以大幅度地降低覆蓋率斷言所造成的負擔。

Since exhaustive functional verification is practically unachievable, coverage metrics are commonly used to avoid unnecessary verification repetitions and to measure the completeness of the verification test suit. However, in a modern hardware-accelerated environment, coverage may be measured across simulator and emulator. Hence, neither conventional coverage techniques performed in simulation nor hardware coverage monitors embedded in emulator can be applied. In this thesis, to measure coverage in a hardware-accelerated environment, we proposed to use coverage assertions which can detect coverage events cross simulator and emulator. In addition, since measuring coverage in a hardware-accelerated may cause hardware and performance overheads, an Assertion Operation Graph (AOG) and graph-based algorithms for the AOG are proposed to optimize the overheads of coverage assertions. We show that multiple coverage metrics can be successfully measured for several designs in the hardware-accelerated environment of Xilinx ISE. Our experimental results also show an encouraging reduction of overhead caused by coverage measurement.

List of Contents V
List of Figures VI
List of Tables VII
Chapter 1 INTRODUCTION 1
Chapter 2 AN ILLUSTRATED EXAMPLE 5
Chapter 3 COVERAGE MEASUREMENT IN A HARDWARE-ACCELERATED ENVIRONMENT 8
3.1 Simulated Coverage Assertion 8
3.2 Emulated Coverage Assertion 10
3.3 Hybrid Coverage Assertion 11
Chapter 4 OPTIMIZATION OF COVERAGE ASSERTIONS 15
4.1 Construction of Assertion Operation Graph 16
4.2 Reduction of Assertion Operation Graph 18
4.3 Partition of Assertion Operation Graph 20
Chapter 5 EXPERIMENTAL RESULTS 25
Chapter 6 CONCLUSIONS 28
REFERENCE 29

[1] R. Grinwald, E. Harel, M. Orgad, S. Ur, and A. Ziv, "User defined coverage-a tool supported methodology for design verification," in Design Automation Conference, 1998, pp. 158 - 163.
[2] O. Lachish, Haifa, Israel IBM Israel Sci. & Technol. Center, E. Marcus, S. Ur, and A Ziv, "Hole analysis for functional coverage data," in Design Automation Conference, 2002, pp. 807 - 812.
[3] Tasiran Serdar and Kurt Keutzer, "Coverage metrics for functional validation of hardware designs," Design & Test of Computers, IEEE, vol. 18, no. 4, pp. 36-45, 2001.
[4] Jing-Yang, and Chien-Nan Jimmy Liu. Jou, "Coverage analysis techniques for hdl design validation," in Asia Pacific conference on Chip design languages, 1999.
[5] M. Bauer, W. Ecker, R. Henftling, and A. Zinn, "A method for accelerating test environments," in EUROMICRO, 1999, pp. 477- 480.
[6] Young-Il Kim and Chong-Min Kyung, "TPartition: testbench partitioning for hardware-accelerated functional verification," Design & Test of Computers, IEEE, vol. 21, no. 6, pp. 484 - 493, 2004.
[7] Young-Il Kim, Wooseung Yang, Young-Su Kwon, and Chong-Min Kyung, "Communication-efficient hardware acceleration for fast functional simulation," in Design Automation Conference, 2004, pp. 293 - 298.
[8] Chin-Lung Chuang, Nat. Central Univ., Jungli, Taiwan Dept. of Electr. Eng., and Chien-Nan Liu, "Hybrid Testbench Acceleration for Reducing Communication Overhead," Design & Test of Computers, IEEE, vol. 28, no. 2, pp. 40 - 51, 2011.
[9] K. Balston, M. Karimibiuki, A.J. Hu, A. Ivanov, and S.J.E. Wilton, "Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs," Computers, IEEE Transactions on , vol. 62, no. 2, pp. 242-246, 2013.
[10] Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar Tommy Bojan, "Functional Coverage Measurements and Results in Post-Silicon Validation of Core™2 Duo Family," in High Level Design Validation and Test Workshop, 2007.
[11] Avi Ziv, "Cross-product functional coverage measurement with temporal properties-based assertions," in Proceedings of the conference on Design, Automation and Test in Europe-Volume 1, 2003.
[12] I. Beer, L. Gluhovsky, S. Keidar, and Y. Wolfsthal. Y. Abarbanel, "FoCs - automatic generation of simulation checkers from formal specification," in Computer Aided Verification Conference, 1999.
[13] SystemVerilog Assertions Tutorial. [Online]. http://www.doulos.com/knowhow/sysverilog/tutorial/assertions/

[14] ISE Design Suite. [Online]. http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm

[15] Open Verification Library Users Site. [Online]. http://www.eda-stds.org/ovl/

[16] S. Das, Indian Inst. of Technol., Kharagpur Dept. of Comput. Sci. & Eng., R. Mohanty, P. Dasgupta, and P.P. Chakrabarti, "Synthesis of System Verilog Assertions," in Design, Automation and Test in Europe, 2006, pp. 1-6.
[17] Mehrdad Reshadi , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau Sumit Gupta, "Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis," in International Symposium on System Synthesis, 2002.
[18] C.M Fiduccia and R.M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions," in Design Automation Conference, 1982.
[19] Ro Oshana. (2002) Introduction to JTAG. [Online]. http://www.embedded.com/electronics-blogs/beginner-s-corner/4024466/Introduction-to-JTAG

[20] Q. Ren , M. Ciesielski , J. Guillot , E. Boutillon D. Gomez-prado, "Optimizing Data Flow Graphs to Minimize Hardware Implementation," in Design, automation and test in Europe, 2009.