電磁干擾(Electromagnetic Disturbance，EMI)源自於基本的物理現象：電生磁，磁又生電，而高頻的電路產生更強的磁場，因此對周遭電路的電磁干擾亦趨嚴重，而傳輸頻率不斷向上提升，其造成的EMI更加嚴重。為符合電磁干擾的安全規定，常見的降低電磁干擾方法主要有外部屏蔽(Shielding)與內部降低頻譜能量(Spread Spectrum)，外部屏蔽成本過高，且在電磁波干擾產生後，才設法解決此問題，治標不治本，無法有效降低電磁干擾；而展頻則是降低電磁干擾源頭的頻譜能量，利用頻率調變將高頻能量平均分散到附近的頻率，此技術為解決電磁干擾的根本之道，成本低廉且效果顯著，被廣泛使用於高速傳輸介面。
此應用於SATA III之展頻時脈產生器利用ΔΣ分數型頻率合成器，並於晶片內部產生符合SATA III 規範之30K Hz三角波，利用此三角波控制除法器的除數，進而達到展頻功能。本論文於傳統除法器的低頻輸出端加上相位內插電路，使得整個除法器的除數解析度下降為0.5，進而使得ΔΣ調變器在平均小數的過程中除數變化縮減為一半，降低ΔΣ調變器造成的量化雜訊。由於此相位內插電路於低頻實現，能降低功率消耗，且電路實現容易只需額外加上取樣用的正反器、選擇最後除法器輸出的多工器，還有一些控制邏輯電路即可。
此展頻時脈產生器使用TSMC 0.18µm 1P6M CMOS 製程，輸出頻率為5.97G~6G Hz，展頻範圍為下展4883ppm。展頻後對電磁干擾的抑制量約為14dB。展頻時脈產生器在1.8 V電壓操作下功率消耗為38mW，整體晶片面積為1090×1330µm^2。

In recent years, lager data storages and higher speed data transfer interfaces have been widely used. As the chip operation speed increasing, the larger electronic-magnetic interference (EMI) will be produced. To restrain the EMI becomes a major issue in high speed application. There are two ways to suppress the EMI: one is to add shielding on the outside of the chip; the other is to use the spread spectrum clocking (SSC) inside the chip. The former is costly and inefficient, the latter can reduce the EMI from its source, so it’s an effective and popular method. The communication systems contain high speed serial link, such as Serial Advanced Technology Attachment (SATA)
This work presents SSCG for SATA3.0. The SSCG utilizes phase switching at the low speed part of the divider to achieve point 5 divider resolution. The phase switching circuit will be added at the end of the integer divider chain. Hence the quantization noise can be repressed and decreasing the power consumption. The switching circuit just contains two resample D flip-flops, a multiplexer to select the final output of the divider and a control logic to manipulate the point 5 divider ratio mechanism.
This chip is fabricated in TSMC 1P6M 0.18um. The output frequency range is from 5.97G to 6G Hz, and the EMI reduction is 14dB with 4883 ppm spreading ratio. The power consumption is 38mW under 1.8V supply voltage. The chip area is 1090×1330µm^2.

Outline

Chapter 1 Introduction - 1 -
1.1 Background - 1 -
1.2 Motivation - 2 -
Chapter 2 SSCG Background - 3 -
2.1 Integer-N PLL - 4 -
2.2 Spread Spectrum Methods - 5 -
2.3 Fractional-N PLL - 6 -
2.3.1 First Order ΔΣ modulator - 9 -
2.3.2 High order ΔΣ modulator - 13 -
2.4 Methods to eliminate quantization noise - 17 -
2.4.1 Current compensation method - 18 -
2.4.2 Phase compensation method - 20 -
2.4.3 Truly fractional divider ratio - 21 -
Chapter 3 PLL Model - 24 -
3.1 Continuous time linear model analysis (S-domain) - 26 -
3.2 PLL phase noise analysis - 31 -
3.3 Discrete time linear model analysis (Z-domain) - 33 -
3.3.1 Time invariant impulse transform - 33 -
3.2.2 Divider down sampling cross couple - 34 -
3.4 Verilog-A behavior model - 34 -
Chapter 4 SSCG Design and Simulation - 35 -
4.1 Brief - 35 -
4.2 Architecture - 36 -
4.3 Circuit simulation - 42 -
4.3.1 Voltage controlled oscillator - 42 -
4.3.2 Phase frequency detector - 48 -
4.3.3 Charge pump - 51 -
4.3.4 Half integer divider - 54 -
4.3.5 Sigma Delta modulator - 57 -
4.3.6 Triangular wave generator - 58 -
4.4 Specification - 61 -
Chapter 5 Simulation results - 62 -
Chapter 6 Conclusion - 70 -
Chapter 7 References - 71 -

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