在論文中提出一個具有高效率節能的健康照顧系統。系統有三個部分所組成的。分別為無線量測節點、行動裝置與雲端伺服器。無線量測節點擷取到的信號傳至附近的電子儀器像是智慧型手機的行動裝置。這些行動會做為資料的中繼站，再以3G 或是WiFi 的方式傳到雲端的伺服器。因為信號必須連續的監測24個小時以上，所以低能量消耗是我們在設計無線量測節點時的主要目標。
在雛型系統中，我們使用商用的元件組成一個無線量測節點。此外我們使用以Android 作業系統的平台開發一個程式，具有可以上傳資料與即時畫圖的功能。在雲端的伺服器我們不僅開發一個低複雜度尋找心電圖上R 點的方法，並且也開發可以預測病人病情的演算法。有了實現雛型系統的經驗，我們可以使用晶片來實現這個系統已讓整體效能更好。
在使用晶片做為無線量測節點的架構中，晶片上具有四個部分，分別為類比放大器、類比數位轉換器、數位信號處理器與無線發射機。在論文中我們集中描述數位信號處理器的部分。數位信號處理器大致是由微處理器、壓縮電路和其他的輔助電路所組成的。其中微處理器是由一個開放原始碼的8051 微處理器所修改的。數位信號處理器的主要功能是作為晶片的主動元件控制其他電路。此外由於無線發射機為最耗電的部分，因此降低所需要傳輸的資料可以減省能量消耗。為了要節省傳輸的資料量，數位信號處理包含了壓縮電路。此外為了要讓功率最低化在數位信號處理器的設計上也是以低功率消耗為考量，像是clock gating的技術。另一方面，為了應付body area network 的需求。在論文中一個多重功能的收發機的設計也被提出。在這個收發機中，數位電路是一個可程式化的處理器可以應付不同模式的解調變的需求。
在論文中所提出的無線感測晶片架構以混和訊號的晶片設計流程實現。此設計流程也會被介紹包括數位電路和類比電路驗證的方法。這個無線感測晶片是以TSMC 0.18 μm 的製程所實現。此晶片的大小為5.29 mm2，在操作電壓在1V和工作頻率為1M Hz 的環境下，數位電路的功率消耗為365 μW，整個晶片的功率為710 μW。

1 Introduction 1
1.1 Backgrounds 1
1.2 Motivation 1
1.3 Main Contributions 2
1.4 Organization of Thesis 3
2 System Description 5
2.1 Overview of Biomedical Signal 5
2.1.1 Biomedical Signal Fundamental 5
2.1.2 MIT-BIH Arrhythmia Database 6
2.2 Review of Traditional Biomedical Signal Measuring Systems 8
2.3 Model Description of Proposed System 9
3 Prototype Implementation for Biomedical Signal Monitoring and Recording 11
3.1 Wireless Sensor Node 12
3.1.1 Front-End Circuits 12
3.1.2 Microprocessor and Analog-to-Digital Converter 15
3.1.3 Wireless Circuits 18
3.2 Mobile Hub 19
3.3 Cloud Sever 20
3.4 System Specification and Comparison 23
4 System-on-Chip Design for Biomedical Signal Monitoring and Recording 25
4.1 Hardware Design 25
4.1.1 Hardware Structure of Chip Version I 26
4.1.2 Microcontroller Improvement 28
4.1.3 Circuits Design for Clock Gating 29
4.1.4 Circuits Design for Data Compression 32
4.1.5 Auxiliary Logic Circuits 37
4.2 Firmware Design 40
4.2.1 Startup 41
4.2.2 Data Recording 41
4.3 Back-End Design 42
4.4 Wireless Body Area Network for Health Monitoring 44
4.4.1 Hardware Design for a General Purpose Transceiver 45
4.4.2 Hardware Structure of Chip Version II 45
4.4.3 Demodulation Logic Circuits 47
5 System-on-Chip Implementation and Integration Results 49
5.1 System-on-Chip Integration Flow 49
5.2 Mixed-Signal System-on-Chip Integration and Co-Verification 50
5.3 ASIC Implementation Results 53
5.3.1 Chip Version I 53
5.3.2 Chip Version II 55
5.3.3 Integration of System-on-Chip for Biomedical Applications 55
5.4 System-on-Chip Simulation and Testing Results 58
5.4.1 Chip Version I 58
5.4.2 Chip Version II 63
5.5 System Specification and Comparison 65
6 Future Work and Conclusion 69
6.1 Future Work 69
6.2 Conclusions 69

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