隨著半導體技術不斷的發展，在單一晶片上可以放置大量的電晶體，進而更複雜的功能就可以被實現。在一個晶片上實現這些複雜系統的一個發展趨勢是將系統分割成很多的子系統，每個子系統可以分別擁有各自不同的電源，不同的時脈頻率，以節省功率消耗並同時保持性能。因此，現今大型的數位電路中，資料在不同的時脈區域之間傳輸已經是一種常態。當非同步的資料 (來自不同時脈區域) 到達的時間是在暫存器的設置-保持(setup-hold)窗口之間時，數據便不能可靠的被接收。因此，就會有可靠度的問題。同步器經常被增加在不同的時脈區域之間用來優化數據傳輸的錯誤。
我們研究的同步器電路通常是由多級數的暫存器所組成，而且我們利用暫存器的參數來表徵平均故障間隔時間(MTBF)。我們發現平均故障間隔時間是由最後一級暫存器的解析時間常數(resolution time)所決定，而且不論這個同步器級數的多寡。廣泛的模擬包含不同的製程、提供的電壓、溫度還有佈局後的模擬和不同世代的製程技術，都證實了這一個發現。基於這一個發現，我們可以優化同步器的設計以增加平均故障間隔時間，同時降低功率消耗或晶片的面積。我們採用的是TSMC 65LP的製程，我們已經觀察到功率消耗可以降低20%，同時保持相同的平均故障間隔時間，或者減少12%的面積在單一三級的混合型同步器電路當中。這個原理可以應用於任何未來的同步器設計。

As the semiconductor technology continue to evolve, large number of transistors can be placed onto a single chip, and thus more complex functions can be implemented. A trend in implementing these complex systems on a chip is to divide the system into subsystems that each subsystem can have different power supply values and different clock frequencies to save power while maintaining the performance. Therefore, data transfer between different clock domains is becoming a norm in today’s large digital IC’s. When the asynchronous data (from different clock domain) arrives within the register’s setup-hold window, the data cannot be reliability received. And thus, it would cause a reliability issue. Synchronizers are usually added in between different domains to minimize data transfer errors.
We investigate the synchronizer circuits, which usually consist of multi-stage registers, and characterize the mean-time-between-failure (MTBF) as a function of register’s parameters. We find that the MTBF is dominated by the resolution time constant of the last stage register, no matter how many stages in the synchronizer. Extensive simulations that include corner conditions, post-layout simulation and different technology generations, all confirm this finding. With this finding, we can optimize the synchronizer design to increase MTBF while reducing power consumptions or area. Using TSMC 65LP technology, we have observed 20% power reduction while maintaining similar MTBF or 12% area reduction in a three stage mixed type synchronizer. This principle can be applied to any future synchronizer design.

中文摘要 i
Abstract ii
誌謝 iii
Content iv
List of Tables ix
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 4
Chapter 2 Metastability 5
2.1 Definition of Metastability 5
2.2 Metastable Event Generation 7
2.2.1 Flip flop timing constrains 7
2.2.2 Metastable behavior 10
2.3 Metastable Properties 11
2.3.1 Regenerative time constant 12
2.3.2 Metastable window Tw 15
2.3.3 Mean time between failure 16
2.4 Related Works of Measurement 17
2.4.1 On-chip measurements 18
2.4.2 Shorting node method 20
2.5 Synchronizer 21
2.6 Summary 24
Chapter 3 Proposed Characterization Method 26
3.1 Proposed simulation method 26
3.1.1 The non-ideal effect 29
3.1.2 Synchronizer simulation 35
3.2 Effective metastable parameters of conventional synchronizer 37
3.3 Effective metastable parameters of mixed type synchronizer 41
3.4 Comparison with existing model 45
3.4.1 MTBF analysis of conventional synchronizer 46
3.4.2 MTBF analysis of mixed type synchronizer 48
3.5 Technology scaling effect 50
Chapter 4 Synchronizer Optimization and Verification 53
4.1 Synchronizer optimization 53
4.1.1 Theory of minimizing resolution time constant 54
4.1.2 Optimization of τ and average power 56
4.1.3 Comparison of mixed type and conventional synchronizer 58
4.2 PVT analysis 61
4.3 Post-layout simulation of flip-flop 64
4.3.1 Post-simulation of delay time 64
4.3.2 Post-simulation of τ 66
4.3.3 Layout effect 67
4.4 Post-layout simulation of mixed type synchronizer 70
4.4.1 TT, FF and SS corners 70
4.4.2 SF and FS corners 73
Chapter 5 Conclusion and Future Works 76
5.1 Conclusion 76
5.2 Future works 78
Reference 79

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