本論文前半段介紹了頻率合成器，並且分析了分數式頻率合成器和整數式頻率合成器的差異及優缺點，在整式式頻率合成器上，如果降低整數N，則會使得參考頻率變大，進而降低頻率的解析度，但也因此提高了頻譜的純淨度，故對於設計者來說，在頻譜的純淨度與頻率的解析度中，必須做取捨，而分數式頻率合成器上，則因為累加器的週期性動作，會產生分數突波，影響頻譜純淨度，故在此介紹使用差異積分調制器如何對這些缺點有何改善影響。
在差異積分調制器方面， 則分別對於一階差異積分調制器，高階差異積分調制器，並分析，在一般情況下，當差異積分調制器的階數提高時，可以得到較好的雜訊整型能力，但若只是單純的增加多個一階調制器的串接數，在運算時會發生不穩定的情況。因此本論文再針對多級差異積分調制器做探討，並比較這三種種差異積分調制器架構置入於分數式頻率合成器中的優缺點，以作為設計時之參考。
論文後半段則利用數位電路設計流程，以台積電TSMC先進技術65nm製程實作了一個採用MASH 1-1 (Muti-Stage Noise Sharping)設計的多級差異積分調製器，利用設計Verilog HDL 程式碼並且經過Synthesis，APR，最後完整驗證Calibre，並且Tape Out，並且將數位電路流程更方便地的建立出來，以供將來使用，除此之外，為了讓其可在高頻電路中獲得應用，致力於提升其時脈速度，其時脈速度在Postsim結果中驗證可達到1G以上。

The first half of this thesis describes the frequency synthesizer, and analyzed the differences between fractional frequency synthesizer and integer frequency synthesizer , and their advantages and disadvantages. About integer frequency synthesizer ,if we decrease integer N, we will increase reference frequency, it will decrease frequency resolution but increase purity of spectral, so designer should make some choice about them, and then we describes how to use the Delta-Sigma Modulator effect to solve these shortcomings.
In the Delta-Sigma Modulator side, respectively , this thesis also discuss first-order Delta-Sigma Modulator, high-order Delta-Sigma Modulator and multi-stage Delta-Sigma Modulator differences and then compare about the advantages and disadvantages when these three kinds of Delta-Sigma Modulators are placed into the fractional frequency synthesizer, as a design reference.
The latter half of this thesis using digital circuit design flow and TSMC 65nm process to implement a MASH 1-1 multi-stage Delta-Sigma Modulator. After Verilog HDL code design, we complete Synthesis, APR, and the validation of Calibre , and then Tape Out. In addition, in order to enable it to get the application in high-frequency circuits, we also committed to enhance its clock speed, and finally its clock speed is be confirmed by Post-sim verification that reach more than 1G Hz.

目錄

Abstract (英文摘要) i
中文摘要 ii
目錄 iv
圖目錄 vi
第一章 緒論 1
1.1 簡介 1
1.2 論文架構 3
第二章 鎖相迴路頻率合成器 4
2.1 整數式頻率合成器 4
第三章 差異積分調制器介紹 9
3.1 差異積分調制器的基本原理 9
3.2 一階差異積分調制器 20
3.3 高 階 差 異 積 分 調 制 器 27
3.4 多 級 雜 訊 整 形 架 構 28
第四章 實驗 32
4.1 軟體介紹 32
4.1.1 Xilinx ISE 32
4.1.2 Design Compiler 32
4.1.3 IC Compiler 34
4.2 分數式差異積分調制器之實作 36
第五章 結論 45
參考文獻 46
附錄 數位電路設計流程建立 50
一．RTL部分 51
二．Synthesis部分 52
三．APR部分 53
四．Calibre部分 57

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