類比數位轉換器為大自然世界與數位電腦之間不可或缺的橋樑，而本論文中的連續漸進式類比數位轉換器主要應用於雷達接收端，接收端接收射頻訊號經由高速取樣降頻過後，再經由基頻放大器執行訊號放大等功能，接著把類比資料交給類比數位轉換器，最後經過轉換送出數位訊號讓電腦分析資料。
本論文實現了一個連續漸進式類比數位轉換器，我們改良了電容矩陣，這其比傳統架構的電容矩陣面積減少50%，且與單調性架構電容矩陣不同的地方則是能夠維持共模電壓不變，這是一個極大優點，避免比較器有隨機偏差電壓的情況發生。經過佈局模擬顯示，利用台積電65奈米的CMOS製程來設計，操作電壓為1V，這個10位元每秒取樣2000萬次的連續漸進式類比數位轉換器有效位元為9.97，DNL與INL為完美結果，平均消耗功率為620μW，每次轉換所消耗的平均能量為30fJ。
本論文一共分為五章，在第一章緒論過後，各章節的大致內容如下：
第一章介紹研究動機。第二章介紹類比數位轉換器幾個重要的參數、連續漸進式類比數位轉換器的原理與概念以及內部幾個核心電路的設計考量，分別是取樣電路、比較器與電容式數位類比轉換器。第三章介紹這次本論文所提出的10位元每秒兩千萬次取樣的連續漸進式類比數位轉換器，與其他架構不同的地方在於此架構能使用比傳統式架構減少50%的電容數目，又能達到共模電壓維持不變，也能有效減少功率消耗，在這章節將會詳細解說。第四章為本論文所提出的連續漸進式類比數位轉換器Post-Simulation的結果。第五章為本論文的總結，以及未來的研究方向及目標。

Analog to digital converter are the essential bridge between nature world and digital world, and this thesis introduces a successive approximation analog to digital converter mainly used in the radar receiver, where the received RF signals are frequency-reduced after high-speed sampling, and then amplified by the baseband amplifier. The signals are then processed by the analog to digital converter and finally the converted digital signal to the computer for data analysis.
In the thesis, we have proposed a successive approximation analog to digital converter, which has been greatly improved the capacitance matrix, making the size 50% less than traditional ones. The ADCs with monotonic structure capacitance matrix of different places are able to maintain the common-mode voltage, which is a huge benefit to avoid comparator from generating random offset voltages. The 10 bits in 20 million samples per second successive approximation analog to digital converter is implemented in a TSMC 65 nm CMOS process. The design is operated in 1V with ENOB 9.97 and perfect DNL, INL. The average power consumption is 620μW, and the average energy consumption is 30fJ each conversion.

中文摘要 i
ABSTRACT(英文摘要) ii
目錄 iii
表目錄 vi
圖目錄 vii
第一章:簡介 1
1.1 研究動機 1
1.2 論文章節組織 2
第二章:研究背景以及相關研究介紹 3
2.1 類比數位轉換器參數 3
2.1.1 量化誤差(Quantization Error) 3
2.1.2 最小解析度(Least Signification Bit) 4
2.1.3 微分線性度(Differential Nonlinearity) 4
2.1.4 遺失碼(Missing Codes) 5
2.1.5 積分線性度(Integral Nonlinearity) 6
2.1.6 偏差(Offset) 6
2.1.7 增益誤差(Gain Error) 7
2.1.8 訊號與雜訊比(Signal-to-Noise Ratio) 8
2.1.9 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 8
2.1.10 有效位元數(Effective Number of Bits) 8
2.1.11 SFDR(Spurious Free Dynamic Range) 8
2.1.12 動態範圍(Dynamic Range) 9
2.1.13 總諧波失真(Total Harmonic Distortion) 9
2.2 連續漸進式類比數位轉換器演算法原理 10
2.3 連續漸進式類比數位轉換器概念 11
2.3.1 SAR ADC概念 11
2.3.2 同步與非同步概念 11
2.4 子電路介紹 13
2.4.1 取樣保持(Sample and Hole)原理及設計考量 13
2.4.2 栓鎖比較器(Latched Comparator) 18
2.4.3 電容式數位類比轉換器(Capacitor DAC) 23
第三章: 65奈米十位元非同步連續漸進式類比數位轉換器設計 25
3.1 架構介紹 25
3.1.1 傳統架構之連續漸進式類比數位轉換器 25
3.1.2 單調性架構之連續漸進式類比數位轉換器 26
3.1.3 本論文所提出之連續漸進式類比數位轉換器 27
3.1.4 切換方式比較 28
3.1.5 切換方式之波型比較 29
3.1.6 本次所提出SAR ADC的流程圖 30
3.2 追蹤及保持(Track and Hole)電路 31
3.2.1 靴帶(Bootstrapped)電路 31
3.2.2 設計過程中的模擬結果 32
3.3 栓鎖比較器(Latched Comparator) 34
3.3.1 比較器(Comparator)設計 34
3.3.2 比較器(Comparator)之非同步邏輯 36
3.3.3 模擬結果 37
3.4 連續漸進式邏輯電路(SAR Logic) 39
3.4.1 時脈產生邏輯 39
3.4.2 控制邏輯(Control Logic) 40
3.5 電容矩陣(Capacitor Array) 42
3.5.1 本次提出之二進制加權電容矩陣(Propose Binary-Weighted Cap Array) 42
3.6 連續漸進式類比數位轉換器(SAR ADC)佈局圖 44
第四章: 65奈米十位元非同步連續漸進式類比數位轉換器模擬結果 46
4.1 Post-Simulation動態參數 46
4.2 類比數位轉換器之效能 49
4.3 比較表 50
第五章: 結論及未來發展 51
參考文獻 52

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