在能源效率逐漸成為系統設計的關鍵考量之一同時，行動裝置及嵌入式系統設計者們也因此急切需要一個有效率並且具有高精確度的功耗估算方法。由於記憶體在製程的進步及系統的需求下，已然逐漸成長為系統中主要的功耗元件之一，我們因此針對現有的記憶體功耗模型進行檢驗並根據一個新的微元件概念來提出一個非常高效率的微元件基礎及資料察覺精確的系統層級記憶體系統功耗估算以改進過往模型精確度的不足及資訊量缺乏的問題。我們提出的方法關鍵在於精確的根據記憶體內部指令來辨認該內部指令啟動時所處發的所有的微元件並對這些微元件的功耗模式進行預校準來評估內部指令的功耗。為了提高精準度，我們更進一步觀察到由於記憶體的電路設計主要在於進行資料內容的傳遞及儲存，所以事實上動態功耗與靜態功耗的值都可以表達成與資料內容線性相關的型式。藉此來觀察並修正資料內容對功耗的影響。憑藉運行時的指令序列及每個指令執行的時間點等資訊，我們查找出各項指令起動的微元件與該微元件相對應的功耗模式，再經過資料察覺來修正功耗內容並得到符合實際運行狀況的能源消耗評估。我們提出的方法得出了非常準確及快速的功耗分析結果，實驗驗證的結果也呈現出我們提出的方法平均僅僅只有1.96%的誤差。

As energy efficiency has become a primary concern, mobile and embedded system designers strongly desire for an efficient and highly accurate power estimation method. Since memory is an increasingly dominant power consumer, we particularly reexamine existing memory power models which are short of being satisfactory and propose a very efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimations. The key of our approach is that we precisely identify the microcomponents activated by internal memory commands and accurately pre-calibrate the power consumption pattern of each microcomponent. To achieve very high accuracy, we further consider data effect by leveraging the fact that memory circuit is mainly doing data passing and both the dynamic and static power value can be refined in a linear fashion. With the runtime command sequence and timing information, we look up the command-activated microcomponents and their corresponding power patterns along with the runtime data-aware refinement. Our approach then generates very accurate and fast power analysis results. Our experiments show that the proposed approach produce accurate results of only 1.96% error rate in average.

1. Introduction 1
2. Related Work 6
3. The Microcomponent-based Approach 9
3.1 Microcomponents 10
3.1.1 Identify Microcomponents 11
3.1.2 Microcomponent Power Model 14
3.1.3 Data effect 16
3.1.4 Verify Data Correction 18
3.1.5 Discussion 19
3.2 Memory Timing Model 19
4. Experimental Results 23
4.1 Verify Accuracy 23
4.2 Trace Simulation 25
4.3 Architecture Evaluation 27
5. Conclusion 28
6. REFERENCES 29

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