在現今的積體電路設計中，減少功率的消耗是一個很重要的設計因素。而正反器在積體電路中是一個很重要的元件，它對電路的速度和功率消耗有很大的影響。在參考文獻中[3]，提到了時脈系統的功率在總功率的消耗中占了30%到60%，而時脈系統是包含時脈網路和正反器中的時脈。雙緣觸發正反器是一個可以在時脈訊號的正緣邊緣和負緣邊緣都可以鎖存數值，因此它的時脈頻率可以減少為一半，而使得明顯降低了時脈網路的功率消耗。
在這篇論文中，我們研發出一個動態雙緣觸發正反器。而和近年來提出的雙緣觸發正反器是有所不同的[3-10]，近年來提出的雙緣觸發正反器是需要在每個的時脈邊緣產生時脈脈衝訊號，而我們的雙緣觸發正反器架構只需要使用原本的時脈訊號，如此一來才能真正節省時脈的功率消耗。非同步的重置功能(reset/set)也簡單各利用了四個電晶體加到我們的雙緣觸發正反器架構上。除此之外，掃描的功能(scan)也同樣的用了兩種方法加到我們的雙緣觸發正反器的架構上，而兩種方法是不同於傳統式的掃描架構。
利用台灣積體電路公司的65奈米低功率製程，我們證明提出的雙緣觸發正反器和正緣觸發傳輸閘正反器(TGFF)在時脈功率的消耗上可以節省達到48%；而和近年來利用在時脈的雙邊緣脈衝產生器設計而成的雙緣觸發正反器[9,14]比較下，我們的雙緣觸發正反器可以在時脈的功率消耗上節省達到60%。

Minimizing power consumption is one of the key design objectives in today’s integrated circuit (IC) designs. Flip-Flops are important elements in integrated circuit which have a large impact on circuit speed and power consumption. It has been shown [3] that 30% to 60% of the total power is consumed by the clock system, that includes clock distribution network and flip-flops. A double edge triggered flip-flop can latch data on both positive and negative edges of the clock signal, thus, the clock frequency can be halved and significantly reducing the clock network power consumption.
In this thesis, we develop a dynamic double edge triggered flip-flop. In contrast to recently published double edge triggered flip-flops [3-10], which need to have pulse signals generated for each clock edges, our flip-flop utilizes clock signal as it is and thus consumes less power. Asynchronous set and reset functions can be easily added to this flip-flop. In addition, scan function can also be added with two approaches.
Using TSMC 65LP technology, we demonstrate that the double edge triggered flip-flop can save 48% of clock power as compared to the positive triggered transmission gate flip-flop; while it saves 60% of clock power compared to the dual edge triggered flip-flop [9,14] which employs a pulse generator to enable double edge trigger capability.

摘要 i
Abstract ii
誌謝 iii
Contents iv
List of Figures vii
List of Tables x
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.2.1 Double edge triggered flip-flop 3
1.2.2 Recently published double edge triggered flip-flops 4
1.3 Thesis organization 5
Chapter 2 D Flip-Flop of SETFF and DETFFs 6
2.1 D Flip-Flop 6
2.2 True Single Phase Clock D Flip-Flop (TSPC) 7
2.3 Double Edge Triggered D Flip-Flops (DETFFs) 8
2.4 DETFF is implemented by pulse generator of the XOR gate and split-out latch 9
2.5 DETFF is implemented by delayed elements of clock 11
2.6 Summary 12
Chapter 3 Proposed Double Edge Triggered D Flip-Flop 14
3.1 Proposed Double Edge Triggered Flip-Flop 14
3.2 Operations 15
3.2.1 Operations 15
3.2.2 Data rises at rising edge triggered clock 17
3.2.3 Data falls at rising edge triggered clock 18
3.2.4 Data rises at falling edge triggered clock 19
3.2.5 Data falls at falling edge triggered clock 20
3.2.6 Waveform of the proposed DETFF operation 21
3.3 Four nodes of the combinational logic 22
3.3.1 Four cases of the combinational signals 23
3.3.2 Best case and worst case in delay time 24
3.3.3 Delay time analysis with four cases 25
3.4 Proposed DETFF with asynchronous Reset/Set 27
3.4.1 Proposed DETFF with asynchronous Reset 27
3.4.2 Proposed DETFF with asynchronous Set 29
3.5 Proposed DETFF with Scan 31
3.5.1 Proposed DETFF with conventional Scan 31
3.5.2 Proposed DETFF with DET Scan (Type 1) 32
3.5.3 Proposed DETFF with TSPC Scan 35
3.6 Summary of three type Scan 36
Chapter 4 Simulations of proposed DETFF 37
4.1 Size optimization for the balanced delay time 37
4.1.1 Algorithm: Minimize the balanced delay time (ck to q) 38
4.2 Setup Time 40
4.3 Hold Time 41
4.4 Power 42
4.5 Input Capacitance 45
4.6 Minimum Clock Frequency (Floating nodes) 46
4.7 Corner conditions 48
4.8 Timing analysis of proposed Scan 50
4.9 Layout of the proposed DETFF 52
Chapter 5 Comparison of other D Flip-Flops 54
5.1 True-Single-Phase-Clocked D Flip-Flop (TSPCFF) 54
5.1.1 Split-Out Latch 54
5.1.2 Size optimization and Delay time (ck to q) 58
5.1.3 Comparison of the timing (TSPCFF vs proposed DETFF) 59
5.1.4 Comparison of the power (TSPCFF vs proposed DETFF) 61
5.1.5 Summary 63
5.2 Master-Slave D Flip-Flop (Transmission Gate Flip-Flop) 64
5.2.1 Comparison of the timing (TGFF vs proposed DETFF) 64
5.2.2 Comparison of the power (TGFF vs proposed DETFF) 66
5.2.3 Summary 68
5.3 Dual edge triggered static pulsed flip flop (DSPFF) [11] 69
5.3.1 Comparison of the timing 70
5.3.2 Comparison of the power 71
5.3.3 Summary 72
5.4 Static differential double edge triggered flip flop [16] 72
5.4.1 Comparison of the timing 73
5.4.2 Comparison of the power 74
5.4.3 Summary 75
5.5 Variations of the dual-pulse clock signals 75
Chapter 6 Conclusions and Future works 78
6.1 Conclusions 78
6.2 Future Works 80
References 81

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