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作者(中文):江俊毅
作者(外文):Chiang, Jiun-Yi
論文名稱(中文):晶片群集相互資訊在多重時脈測試之應用
論文名稱(外文):Chip Clustering with Mutual Information on Multiple Clock Tests and its Application to Yield Tuning
指導教授(中文):劉靖家
指導教授(外文):Liou, Jing-Jia
口試委員(中文):王行健
陳竹一
口試委員(外文):Wang, Sying-Jyan
Chen, Zu-Yi
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:100061588
出版年(民國):103
畢業學年度:102
語文別:英文
論文頁數:49
中文關鍵詞:超大積體電路測試製程變異
外文關鍵詞:VLSITestingProcess variation
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隨著互補式金屬氧化物半導體製程技術進入深次微米時代,製程變異以及生
產過程缺陷嚴重得影響著產品的良率,截至目前為止,並沒有一套有效率的方法
去輔助設計者分析製程變異所帶來的影響。製程變異主要分成兩種,隨機性製程
變異以及系統性製程變異,其中系統性製程變異對於光罩、蝕刻與佈局有很高的
相依性,我們針對系統性變異來加以分析。
在本篇論文中,我們提出一套多重時脈測試的方法,先挑取受到系統性製程
變異影響的路徑,在利用多重測試時脈加以區分晶片,再使用分群的方法,將受
到相似製程變異的晶片分群再一起,並應用了SAT-based 的方法找到相對應調整
過後的電壓值,並建立分類器,去修復受到製程變異影響造成無法達到標準的晶
片,由於SAT-based 的方法需要更大量的測試時脈,所以使用建立分類器的方法
只需要2~3 個測試時脈可以大量節省測試成本(約省下原來的90%)並同時達到接
近SAT-based 的良率。
利用調整電壓來加速晶片已達到修復目的,勢必會造成電量上的消耗,
但經過我們的實驗結果顯示,只要利用2 到3 個測試時脈,就可以達到88%~99%
的良率,而且電量消耗只多出4%~25%,相較於最差的情況(所有列電壓都拉高)
需額外增加50%電量,我們的方法可以找到較低的電量消耗就可以達到很高的良
率。
1 Introduction 7
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Preview of our method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Background 14
2.1 Process variations and sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Tunable circuit design and tuning algorithm . . . . . . . . . . . . . . . . . . . . . 15
2.3 Test path selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Building the classification model using SVM . . . . . . . . . . . . . . . . . . . . 20
2.5 MBSAS clustering algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 Mutual information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Proposed Methods 25
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Multiple test clocks selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4 Flow of classifier-based yield tuning . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Clustering-based voltage merging . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Feature reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Experimental Result 36
4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.1 Process Variation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.2 Test cost model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.3 Process variation experiment . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.1 Test cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.2 Multiple test clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.3 Different type variation model . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Conclusions and Future Work 46
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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