本論文提出了一個十一位元低功耗連續近似類比數位轉換器，可應用於無線通訊系統，並且使用校正與每周期比較兩位元之技術(2b/C)。
所提出的類比數位轉換器為了實現較高的操作速度，使用了每周期比較兩位元的方法，得到兩倍的操作速度，由於此方法需要使用三個比較器，其偏移會導致線性度下降，這裡使用了比較器偏移校正電路來消除三個比較器的偏移並且得到了明顯改善。為了實現每周期比較兩位元的方法，電路中有一組額外的數位類比轉換器(DAC)用來產生參考電壓，為了解決兩組數位類比轉換器之不匹配以及比較器的動態偏移，在數位類比轉換器中加入了冗餘位元，此方法比起二分搜尋法有較大的搜索範圍，因此能容忍比較過程中一定大小的錯誤量，。此外，本論文還提出了一個兩階段式數位類比轉換器(two-step DAC)切換方法來降低耗能，藉由組合每周期比較兩位元以及每周期比較一位元的切法，可以降低用來產生參考電壓之數位類比轉換器的解析度，因此能降低切換功耗與面積，改善能源效率。
此架構使用台積電標準90 奈米1P9M 互補式金氧半導體製程製作，晶片面積為160 x 550um2，操作電壓0.9 伏特，在一千萬赫茲的取樣頻率及一萬赫茲的輸入訊號頻率下得到SNDR 為55.3dB 對應到8.9 個有效位元，功率消耗為108微瓦，等校的figure of merit (FoM) 22.6fJ/conversion-step。

This thesis proposed an 11-bit power-efficient 2 bits per cycle (2b/C) successive approximation register (SAR) analog-to-digital converter (ADC) with calibration for wireless communication systems.
To achieve a higher operation speed, a 2b/cycle topology is adopted in this work. The Multi-bit per cycle ADC requires multiple comparators and reference voltage to perform the technique. To realize the 2b/C method, an additional digital-to-analog converter (DAC) is needed to generate a reference voltage. The mismatch between the reference DAC and signal DAC will degrade the linearity. The solution is to add redundancy bits to tolerate the error during the AD conversion. Since the comparator offsets will cause linearity error and degradation of ADC performance, an offset calibration is used to cancel the offsets and keep an acceptable linearity. Besides, a 2-step DAC configuration is proposed to reach a lower power and area. Combine the 2b/C DAC and 1b/C DAC, the resolution of reference DAC can be reduced. Hence, the DAC power and area are decreased.
This prototype was fabricated by TSMC 90nm 1P9M CMOS technology and the core area is 160x550um2. At a 0.9V supply and a 10MS/s sampling rate with a input frequency of 10kHz, the ADC achieves a SNDR of 55.4dB and a corresponding ENOB of 8.9b. The power consumption is 108 W and it achieves a FoM of 22.6 fJ/conv-step.

ABSTRACT II
CONTENTS III
LIST OF FIGURES VI
LIST OF TABLES IX
CHAPTER 1 INTRODUCTION 1
1.1 ARCHITECTURE SELECTION 2
1.2 ADC PERFORMANCE METRICS 3
1.2.1 Resolution 3
1.2.2 Differential and Integral Nonlinearity (DNL, INL) 4
1.2.3 Signal-to-Noise Ratio (SNR) 4
1.2.4 Signal-to-Noise-and-Distortion Ratio (SNDR) 4
1.2.5 Effective Number-of-Bits (ENOB) 5
1.2.6 Figure of Merit (FoM) 5
1.3 MOTIVATION 5
1.4 TARGET SPECIFICATIONS 6
1.5 THESIS ORGANIZATIONS 6
CHAPTER 2 SUCCESSIVE APPROXIMATION REGISTER (SAR) ADC OVERVIEW 7
2.1 CONVENTIONAL SINGLE-ENDED SAR ADC 7
2.2 SAMPLING NETWORK 8
2.2.1 On-Resistance of MOS Switch 9
2.2.2 Charge Injection 9
2.2.3 Clock Feedthrough 10
2.2.4 KT/C noise 10
2.3 DIGITAL-TO-ANALOG CONVERTER 11
2.3.1 DAC parasitic Capacitance 11
2.3.2 DAC Capacitor Mismatch 12
2.4 COMPARATOR 13
2.4.1 Input Offset 13
2.4.2 Kickback noise 14
2.5 DIGITAL SAR CONTROL LOGIC 14
2.6 SUMMARY 16
CHAPTER 3 ADC DESIGN CONSIDERATIONS 17
3.1 DIFFERENTIAL SAR ADC 17
3.2 CDAC SWITCHING ENERGY 18
3.2.1 Conventional DAC Switching 18
3.2.2 Monotonic DAC Switching [9] 21
3.2.3 Vcm-based DAC Switching [8] 23
3.2.4 Splitting-Monotonic DAC Switching [29] 25
3.2.5 Concept of the 2b/cycle DAC switching and proposed method 27
3.3 SAMPLE AND HOLD DESIGN CONSIDERATION 29
3.4 COMPARATOR DESIGN CONSIDERATION 29
3.5 DIGITAL SAR CONTROL DESIGN CONSIDERATION 30
3.6 SUMMARY 30
CHAPTER 4 ADC IMPLEMENTATION 31
4.1 ADC ARCHITECTURE AND CDAC DESIGN 31
4.2 SAMPLE-AND-HOLD CIRCUIT DESIGN 38
4.3 DYNAMIC COMPARATOR DESIGN 39
4.4 DIGITAL SAR CONTROL LOGIC DESIGN 40
4.5 COMPARATOR OFFSET CALIBRATION 41
4.6 POST-LAYOUT SIMULATION 44
4.7 SUMMARY 44
CHAPTER 5 MEASUREMENT RESULTS 46
5.1 MEASUREMENT ENVIRONMENT SETUP 46
5.2 MEASUREMENT PARAMETER SETUP 46
5.3 STATIC PERFORMANCE 47
5.4 DYNAMIC PERFORMANCE 48
5.5 PERFORMANCE DISCUSSION 49
5.6 SUMMARY 57
CHAPTER 6 CONCLUSION AND FUTURE WORK 59
6.1 CONCLUSION 59
6.2 FUTURE WORK 59
BIBLIOGRAPHY 60

[1] Razak, Z., et al., "Nyquist-rate analog-to-digital converter specification for Zero-IF UMTS receiver," Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on , vol., no., pp.2338,2341, 18-21 May 2008
[2] B. Murmann, “ADC Performance Survey 1997-2014, ” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
[3] Verbruggen, B., et al., "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS," Solid-State Circuits, IEEE Journal of , vol.47, no.12, pp.2880,2887, Dec. 2012
[4] Chen, S.-W., et al., "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13/spl mu/m CMOS," Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International , vol., no., pp.2350,2359, 6-9 Feb. 2006
[5] Hyeok-Ki Hong, et al., "An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International , vol., no., pp.470,471, 17-21 Feb. 2013
[6] Hegong Wei, et al., "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC," Solid-State Circuits, IEEE Journal of , vol.47, no.11, pp.2763,2772, Nov. 2012
[7] H.-Y. Huang, et al., "A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching," Circuits and Systems (ISCAS), 2012 IEEE International Symposium on , vol., no., pp.2353,2356, 20-23 May 2012
[8] Y. Zhu, et al., “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.
[9] C.-C. Liu, et al., “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
[10] G.-Y. Huang, et al., "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.21, no.3, pp.584,588, March 2013
[11] W.-Y. Pang, et al., "A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications," Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian , vol., no., pp.149,152, 16-18 Nov. 2009
[12] C.-H. Kuo, et al., "A high energy-efficiency SAR ADC based on partial floating capacitor switching technique," ESSCIRC (ESSCIRC), 2011 Proceedings of the , vol., no., pp.475,478, 12-16 Sept. 2011
[13] Kandala, M.; Sekar, R., et al., "A low power charge-redistribution ADC with reduced capacitor array," Quality Electronic Design (ISQED), 2010 11th International Symposium on , vol., no., pp.44,48, 22-24 March 2010
[14] Ginsburg, B.P., et al., "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC," Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on , vol., no., pp.184,187 Vol. 1, 23-26 May 2005
[15] Binhee Kim, et al., "An energy-efficient dual sampling SAR ADC with reduced capacitive DAC," Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on , vol., no., pp.972,975, 24-27 May 2009
[16] Zhangming Zhu, et al., "VCM-based monotonic capacitor switching scheme for SAR ADC," Electronics Letters , vol.49, no.5, pp.327,329, February 28 2013
[17] C.-Y. Liou, et al., "A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International , vol., no., pp.280,281, 17-21 Feb. 2013
[18] J.-Y. Lin, et al., "A 0.05mm2 0.6V 500kS/s 14.3fJ/conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager," Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian , vol., no., pp.165,168, 12-14 Nov. 2012
[19] Figueiredo, P.M., et al., "Kickback noise reduction techniques for CMOS latched comparators," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.53, no.7, pp.541,545, July 2006
[20] Hoonki Kim, et al., "A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array," Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on , vol., no., pp.1,4, 8-10 Dec. 2008
[21] S.-S. Wong, et al., "Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs," SoC Design Conference (ISOCC), 2009 International , vol., no., pp.333,336, 22-24 Nov. 2009
[22] G.-Y. Huang, et al., "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian , vol., no., pp.157,160, 16-18 Nov. 2009
[23] Harpe, P., et al., "A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.388,389, 7-11 Feb. 2010
[24] Geelen, G., et al., "A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step," Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International , vol., no., pp.782,791, 6-9 Feb. 2006
[25] Boulemnakher, M., ea al., "A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS," Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International , vol., no., pp.250,611, 3-7 Feb. 2008
[26] C.-C. Liu, et al., "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no., pp.386,387, 7-11 Feb. 2010
[27] Y.-Z. Lin, et al., "A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.60, no.3, pp.570,581, March 2013
[28] van Elzakker, M., et al., "A 10-bit Charge-Redistribution ADC Consuming 1.9 W at 1 MS/s," Solid-State Circuits, IEEE Journal of , vol.45, no.5, pp.1007,1015, May 2010
[29] S.-H. Wan, et al., "A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers," Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian , vol., no., pp.293,296, 11-13 Nov. 2013